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7643 Datasheet(PDF) 379 Page - Renesas Technology Corp |
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7643 Datasheet(HTML) 379 Page - Renesas Technology Corp |
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379 / 424 page ![]() 7643 Group REJ09B0133-0200 APPENDIX 3.5 Control registers Rev.2.00 Aug 28, 2006 page 56 of 98 UART mode register b7 b6 b5 b4 b3 b2 b1 b0 UART mode register (UMOD : address 3016) b 0 0 1 2 4 Name 0 Functions At reset R W 0 0 0 0 0 UART clock prescaling select bits (PS) Parity select bit (PMD) Parity enable bit (PEN) Stop bit length select bit (STB) b2b1 0 0 : φ/1 0 1 : φ/8 1 0 : φ/32 1 1 : φ/256 0 : 1 stop bit 1 : 2 stop bits 0 : Even parity 1 : Odd parity 0 : Parity checking disabled 1 : Parity checking enabled 5 0 UART character length select bit (LE1, 0) 6 7 0 3 b7b6 0 0 : 7 bits 0 1 : 8 bits 1 0 : 9 bits 1 1 : Not available Nothing is arranged for this bit. Fix this bit to “0”. UART baud rate generator b7 b6 b5 b4 b3 b2 b1 b0 UART baud rate generator (UBRG: address 3116) b 0 Undefined Functions At reset R W 1 Undefined 2 Undefined 3 Undefined 4 Undefined 5 Undefined 6 Undefined 7 Undefined qThe UBRG determines the baud rate for transfer. qThis is a 8-bit counter with its reload register. This generator divides the frequency of the count source by 1/(n + 1), where “n” is the value written to the UBRG. Fig. 3.5.23 Structure of Timer UART mode register Fig. 3.5.24 Structure of UART baud rate generator |
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