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7643 Datasheet(PDF) 374 Page - Renesas Technology Corp |
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7643 Datasheet(HTML) 374 Page - Renesas Technology Corp |
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374 / 424 page ![]() 7643 Group REJ09B0133-0200 APPENDIX 3.5 Control registers Rev.2.00 Aug 28, 2006 page 51 of 98 Port P2 pull-up control register b7 b6 b5 b4 b3 b2 b1 b0 Port P2 pull-upt control register (PUP2 : address 1216) b 0 1 2 4 Name 0 Functions At reset R W 0 0 0 0 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 5 0 0 : Disabled 1 : Enabled 6 0 Port P26 pull-up control bit 0 : Disabled 1 : Enabled 7 0 Port P27 pull-up control bit 0 : Disabled 1 : Enabled Port P20 pull-up control bit Port P21 pull-up control bit Port P22 pull-up control bit Port P23 pull-up control bit Port P24 pull-up control bit Port P25 pull-up control bit 3 USB control register b7 b6 b5 b4 b3 b2 b1 b0 USB control register (USBC : address 1316) b 0 1 2 3 4 5 6 7 Name 0 Functions At reset R W 0 0 0 0 0 0 USB line driver current control bit (USBC3) USB line driver supply enable bit (USBC4) (Note 2) 0 : In default state after power-on/reset 1 : In default state after USB reset signal received (Note 1) 0 : High current mode 1 : Low current mode 0 : Line driver disabled 1 : Line driver enabled 0 : 48 MHz clock to the USB block disabled 1 : 48 MHz clock to the USB block enabled USB enable bit (USBC7) 0 : USB block disabled (Note 3) 1 : USB block enabled USB default state selection bit (USBC1) USB clock enable bit (USBC5) 0 0 0 0 Notes 1: Without regard to this bit, USB internal registers (address 005016 to 005F16) go into the states at reset (default) at the same time when USB reset is detected. 2: When using the MCU in Vcc = 3.3 V, set this bit to “0” and disable the built-in DC- DC converter. 3: Setting this bit to 0” causes the contents of all USB registers to have the values at reset. Nothing is arranged for this bit. Fix this bit to “0”. Nothing is arranged for this bit. Fix this bit to “0”. Nothing is arranged for this bit. Fix this bit to “0”. Fig. 3.5.15 Structure of Port P2 pull-up control register Fig. 3.5.16 Structure of USB control register |
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