7643 datasheet(373/424 Pages) RENESAS

373 / 424 page

7643 Group

REJ09B0133-0200

APPENDIX

3.5 Control registers

Rev.2.00

Aug 28, 2006

page 50 of 98

Port control register

b7 b6 b5 b4 b3 b2 b1 b0

Port control register

(PTC : address 1016)

Name

Functions

At reset R W

0 : Disabled

1 : Enabled

0 : Disabled

1 : Enabled

0 : Disabled

1 : Enabled

0 : Disabled

1 : Enabled

0 : Disabled

1 : Enabled

0 : Disabled

1 : Enabled

Port P2 input level select

bit

0 : Reduced VIHL level input (Note 2)

1 : CMOS level input

Port P0 to P3 slew rate

control bit (Note 1)

Port P4 slew rate control

bit (Note 1)

Port P5 slew rate control

bit (Note 1)

Port P6 slew rate control

bit (Note 1)

Port P7 slew rate control

bit (Note 1)

Port P8 slew rate control

bit (Note 1)

Notes 1: The slew rate function can reduce di/dt by modifying an internal buffer structure.

2: The characteristics of VIHL level is basically the same as that of TTL level. But, its

switching center point is a little higher than TTL’s.

Nothing is arranged for this bit.

Fix this bit to “0”.

Interrupt polarity select register

b7 b6 b5 b4 b3 b2 b1 b0

Interrupt polarity select register

(IPOL : address 1116)

Name

Functions

At reset R W

INT0 interrupt edge select

bit

0 : Falling edge active

1 : Rising edge active

0 : Falling edge active

1 : Rising edge active

INT1 interrupt edge select

bit

00 0 0 00

Nothing is arranged for these bits.

Fix these bits to “0”.

Fig. 3.5.13 Structure of Port control register

Fig. 3.5.14 Structure of Interrupt polarity select register

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