7643 datasheet(391/424 Pages) RENESAS

391 / 424 page

7643 Group

REJ09B0133-0200

APPENDIX

3.5 Control registers

Rev.2.00

Aug 28, 2006

page 68 of 98

Fig. 3.5.38 Structure of USB interrupt status register 1

USB interrupt status register 1

b7 b6 b5 b4 b3 b2 b1 b0

USB interrupt status register 1

(USBIS1 : address 5216)

Name

Functions

At reset R W

USB endpoint 1 IN

interrupt status flag

(INTST2)

USB endpoint 1 OUT

interrupt status flag

(INTST3)

0 : Except the following conditions

1 : Set at any one of the following

conditions:

• A packet data of endpoint 0 is

successfully received

• A packet data of endpoint 0 is

successfully sent

• DATA_END bit of endpoint 0 is

cleared to “0”

• FORCE_STALL bit of endpoint 0 is

set to “1”

• SETUP_END bit of endpoint 0 is set

to “1”.

0 : Except the following conditions

1 : Set at which of the following

condition:

• A packet data of endpoint 1 is

successfully sent

USB endpoint 2 IN

interrupt status flag

(INTST4)

0 : Except the following conditions

1 : Set at which of the following

condition:

• A packet data of endpoint 2 is

successfully sent

USB endpoint 0 interrupt

status flag (INTST0)

Nothing is arranged for this bit. Fix this bit to “0”.

Nothing arranged for these bits.

Fix these bits to “0”.

✽

0 : Except the following conditions

1 : Set at any one of the following

conditions:

• A packet data of endpoint 1 is

successfully received

• FORCE_STALL bit of endpoint 1 is set

to “1”.

USB endpoint 2 OUT

interrupt status flag

(INTST5)

✽

0 : Except the following conditions

1 : Set at any one of the following

conditions:

• A packet data of endpoint 2 is

successfully received

• FORCE_STALL bit of endpoint 2 is set

to “1”.

✽: “0” can be set by software, but “1” cannot be set.

To clear the bit set to “1”, write “1” to the bit.

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