7643 datasheet(393/424 Pages) RENESAS

393 / 424 page

7643 Group

REJ09B0133-0200

APPENDIX

3.5 Control registers

Rev.2.00

Aug 28, 2006

page 70 of 98

Fig. 3.5.40 Structure of USB interrupt enable register 1

Fig. 3.5.41 Structure of USB interrupt enable register 2

Nothing arranged for this bit. Fix this bit to “0”.

USB interrupt enable register 1

b7 b6 b5 b4 b3 b2 b1 b0

USB interrupt enable register 1

(USBIE1 : address 5416)

Name

Functions

At reset R W

USB endpoint 1 IN interrupt

enable bit (INTEN2)

USB endpoint 1 OUT inter-

rupt enable bit (INTEN3)

0 : Disabled

1 : Enabled

0 : Disabled

1 : Enabled

0 : Disabled

1 : Enabled

USB endpoint 2 OUT inter-

rupt enable bit (INTEN5)

USB endpoint 0 interrupt

enable bit (INTEN0)

USB endpoint 2 IN interrupt

enable bit (INTEN4)

0 : Disabled

1 : Enabled

0 : Disabled

1 : Enabled

Nothing is arranged for these bits. When these bits are read out, the

contents are undefined. These bits are “0” at write.

Nothing is arranged for these bits. Fix these bits to “0”.

USB interrupt enable register 2

b7 b6 b5 b4 b3 b2 b1 b0

USB interrupt enable register 2

(USBIE2 : address 5516)

Name

Functions

At reset R W

Nothing is arranged for this bit. Fix this bit to “1”.

Nothing is arranged for this bit. Fix this bit to “0”.

USB suspend/resume

interrupt enable bit (INTEN15)

0 : Disabled

1 : Enabled

Nothing is arranged for these bits. When these bits are read out,

the contents are undefined. These bits are “0” at write.

Nothing is arranged for this bit. When this bit is read out, the contents

are undefined. This bit is “0” at write.

7643 Datasheet(PDF) 393 Page - Renesas Technology Corp

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