7643 datasheet(400/424 Pages) RENESAS

400 / 424 page

7643 Group

REJ09B0133-0200

APPENDIX

3.5 Control registers

Rev.2.00

Aug 28, 2006

page 77 of 98

Flash memory control register

b7 b6 b5 b4 b3 b2 b1 b0

Flash memory control register

(FMCR : address 6A16)

Name

Functions

At reset R W

CPU rewrite mode select

bit (FLCA1) (Note 2)

Flash memory reset bit

(FLCA3) (Note 3)

User ROM area / Boot

ROM area select bit

(FLCA4) (Note 4)

Reserved bits

CPU rewrite mode entry

flag (FLCA2)

0 : Busy (being programmed or erased)

1 : Ready

0 : Normal mode (Software commands

invalid)

1 : CPU rewrite mode (Software

commands acceptable)

0 : Normal mode

1 : CPU rewrite mode

0 : Normal operation

1 : Reset

0 : Interrupt disabled

1 : Interrupt enabled

RY/BY status flag

(FLCA0)

Indefinite at read. Write “0” at write.

Notes 1: The contents of flash memory control register are “XXX00001” just after reset

release.

In the mask ROM version this area is reserved, so that do not write any data to

this address.

2: For this bit to be set to “1”, the user needs to write “0” and then “1” to it in

succession. If it is not this procedure, this bit will not be set to ”1”. Additionally, it

is required to ensure that no interrupt will be generated during that interval.

Use the control program in the area except the built-in flash memory for write to

this bit.

3: This bit is valid when the CPU rewrite mode select bit is “1”. Set this bit 3 to “0”

subsequently after setting bit 3 to “1”.

4: Use the control program in the area except the built-in flash memory for write to

this bit.

Fig. 3.5.50 Structure of Flash memory control register

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