MC68HC705C9ACFN datasheet(75/157 Pages) FREESCALE

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General Release Specification

Timer I/O Registers

MC68HC705C9A — Rev. 2.0

Capture/Compare Timer

8.4.5 Input Capture Registers (ICRH and ICRL)

When a selected edge occurs on the TCAP pin, the current high and low

bytes of the 16-bit counter are latched into the input capture registers.

Reading ICRH before reading ICRL inhibits further capture until ICRL is

read. Reading ICRL after reading the status register clears the input

capture flag (ICF). Writing to the input capture registers has no effect.

Figure 8-6. Input Capture Registers (ICRH and ICRL)

NOTE:

To prevent interrupts from occurring between readings of ICRH and

ICRL, set the interrupt flag in the condition code register before reading

ICRH, and clear the flag after reading ICRL.

ICRH

$0014

Bit 7

Bit 0

Read:

BIT15

BIT14

BIT13

BIT12

BIT11

BIT10

BIT9

BIT8

Write:

ICRL

$0015

Bit 7

Bit 0

Read:

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

Write:

RESET DOES NOT AFFECT THE INPUT CAPTURE REGISTERS

= Unimplemented

Freescale Semiconductor, Inc.

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