MC68HC705C9ACFN datasheet(95/157 Pages) FREESCALE

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General Release Specification

SCI I/O Registers

MC68HC705C9A — Rev. 2.0

Serial Communications Interface (SCI)

the SCDR. Reset sets the TC bit. Software must initialize the TC bit

to logic zero to avoid an instant interrupt request when turning the

transmitter on.

1 = No transmission in progress

0 = Transmission in progress

RDRF — Receive Data Register Full

This clearable, read-only flag is set when the data in the receive shift

interrupt request if the RIE bit in the SCCR2 is also set. Clear the

RDRF bit by reading the SCSR with RDRF set and then reading the

SCDR.

1 = Received data available in SCDR

0 = Received data not available in SCDR

IDLE — Receiver Idle

This clearable, read-only flag is set when 10 or 11 consecutive logic

ones appear on the receiver input. IDLE generates an interrupt

request if the ILIE bit in the SCCR2 is also set. Clear the ILIE bit by

reading the SCSR with IDLE set and then reading the SCDR.

1 = Receiver input idle

0 = Receiver input not idle

OR — Receiver Overrun

This clearable, read-only flag is set if the SCDR is not read before the

receive shift register receives the next word. OR generates an

interrupt request if the RIE bit in the SCCR2 is also set. The data in

the shift register is lost, but the data already in the SCDR is not

affected. Clear the OR bit by reading the SCSR with OR set and then

reading the SCDR.

1 = Receive shift register full and RDRF = 1

0 = No receiver overrun

NF — Receiver Noise Flag

This clearable, read-only flag is set when noise is detected in data

received in the SCI data register. Clear the NF bit by reading the

SCSR and then reading the SCDR.

1 = Noise detected in SCDR

0 = No noise detected in SCDR

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MC68HC705C9ACFN Datasheet(PDF) 95 Page - Freescale Semiconductor, Inc