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MC68HC705C9ACFN Datasheet(PDF) 77 Page - Freescale Semiconductor, Inc |
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MC68HC705C9ACFN Datasheet(HTML) 77 Page - Freescale Semiconductor, Inc |
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77 / 157 page  General Release Specification Timer During Wait Mode MC68HC705C9A — Rev. 2.0 Capture/Compare Timer 8.5 Timer During Wait Mode The CPU clock halts during the wait mode, but the timer remains active. If interrupts are enabled, a timer interrupt will cause the processor to exit the wait mode. 8.6 Timer During Stop Mode In the stop mode, the timer stops counting and holds the last count value if STOP is exited by an interrupt. If STOP is exited by RESET, the counters are forced to $FFFC. During STOP, if at least one valid input capture edge occurs at the TCAP pins, the input capture detect circuit is armed. This does not set any timer flags or wake up the MCU, but if an interrupt is used to exit stop mode, there is an active input capture flag and data from the first valid edge that occurred during the stop mode. If RESET is used to exit stop mode, then no input capture flag or data remains, even if a valid input capture edge occurred. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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