SPMCK16Z4MPV16 datasheet(227/500 Pages) FREESCALE

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M68HC16 Z SERIES

QUEUED SERIAL MODULE

USER’S MANUAL

9-17

Data transfer is synchronized with the internally-generated serial clock SCK. Control

bits, CPHA and CPOL, in SPCR0, control clock phase and polarity. Combinations of

CPHA and CPOL determine upon which SCK edge to drive outgoing data from the

MOSI pin and to latch incoming data from the MISO pin.

Baud rate is selected by writing a value from two to 255 into SPBR[7:0] in SPCR0. The

QSPI uses a modulus counter to derive the SCK baud rate from the MCU system

clock.

The following expressions apply to the SCK baud rate:

Giving SPBR[7:0] a value of zero or one disables the baud rate generator and SCK

assumes its inactive state.

The DSCK bit in each command RAM byte inserts either a standard (DSCK = 0) or

user-specified (DSCK = 1) delay from chip-select assertion until the leading edge of

the serial clock. The DSCKL field in SPCR1 determines the length of the user-defined

delay before the assertion of SCK. The following expression determines the actual de-

lay before SCK:

where DSCKL[6:0] equals {1, 2, 3,..., 127}.

When DSCK equals zero, DSCKL[6:0] is not used. Instead, the PCS valid-to-SCK

transition is one-half the SCK period.

There are two transfer length options. The user can choose a default value of eight

bits, or a programmed value from eight to sixteen bits, inclusive. The programmed val-

ue must be written into BITS[3:0] in SPCR0. The BITSE bit in each command RAM

byte determines whether the default value (BITSE = 0) or the BITS[3:0] value (BITSE

= 1) is used. Table 9-3 shows BITS[3:0] encoding.

SCK Baud Rate

sys

SPBR[7:0]

-------------------------------------

SPBR[7:0]

sys

SCK Baud Rate Desired

--------------------------------------------------------------------------

PCS to SCK Delay

DSCKL[6:0]

sys

-------------------------------

Freescale Semiconductor, Inc.

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