SPMCK16Z4MPV16 datasheet(229/500 Pages) FREESCALE

229 / 500 page

M68HC16 Z SERIES

QUEUED SERIAL MODULE

USER’S MANUAL

9-19

QSPI operation is initiated by setting the SPE bit in SPCR1. Shortly after SPE is set,

the QSPI executes the command at the command RAM address pointed to by

NEWQP. Data at the pointer address in transmit RAM is loaded into the data serializer

and transmitted. Data that is simultaneously received is stored at the pointer address

in receive RAM.

When the proper number of bits have been transferred, the QSPI stores the working

queue pointer value in CPTQP, increments the working queue pointer, and loads the

next data for transfer from transmit RAM. The command pointed to by the incremented

working queue pointer is executed next, unless a new value has been written to

NEWQP. If a new queue pointer value is written while a transfer is in progress, that

transfer is completed normally.

When the CONT bit in a command RAM byte is set, PCS pins are continuously driven

to specified states during and between transfers. If the chip-select pattern changes

during or between transfers, the original pattern is driven until execution of the follow-

ing transfer begins. When CONT is cleared, the data in register PORTQS is driven be-

tween transfers. The data in PORTQS must match the inactive states of SCK and any

peripheral chip-selects used.

When the QSPI reaches the end of the queue, it sets the SPIF flag. SPIF is set during

the final transfer before it is complete. If the SPIFIE bit in SPCR2 is set, an interrupt

request is generated when SPIF is asserted. At this point, the QSPI clears SPE and

stops unless wrap-around mode is enabled.

9.3.5.2 Master Wrap-Around Mode

Wrap-around mode is enabled by setting the WREN bit in SPCR2. The queue can

wrap to pointer address $0 or to the address pointed to by NEWQP, depending on the

state of the WRTO bit in SPCR2.

In wrap-around mode, the QSPI cycles through the queue continuously, even while

the QSPI is requesting interrupt service. SPE is not cleared when the last command

in the queue is executed. New receive data overwrites previously received data in re-

ceive RAM. Each time the end of the queue is reached, the SPIF flag is set. SPIF is

not automatically reset. If interrupt-driven QSPI service is used, the service routine

must clear the SPIF bit to end the current interrupt request. Additional interrupt re-

quests during servicing can be prevented by clearing SPIFIE, but SPIFIE is buffered.

Clearing it does not end the current request.

Wrap-around mode is exited by clearing the WREN bit or by setting the HALT bit in

SPCR3. Exiting wrap-around mode by clearing SPE is not recommended, as clearing

SPE may abort a serial transfer in progress. The QSPI sets SPIF, clears SPE, and

stops the first time it reaches the end of the queue after WREN is cleared. After HALT

is set, the QSPI finishes the current transfer, then stops executing commands. After

the QSPI stops, SPE can be cleared.

Freescale Semiconductor, Inc.

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SPMCK16Z4MPV16 Datasheet(PDF) 229 Page - Freescale Semiconductor, Inc

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