SPMCK16Z4MPV16 datasheet(228/500 Pages) FREESCALE

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QUEUED SERIAL MODULE

M68HC16 Z SERIES

9-18

USER’S MANUAL

Delay after transfer can be used to provide a peripheral deselect interval. A delay can

also be inserted between consecutive transfers to allow serial A/D converters to com-

plete conversion. Writing a value to DTL[7:0] in SPCR1 specifies a delay period. The

DT bit in each command RAM byte determines whether the standard delay period (DT

= 0) or the user-specified delay period (DT = 1) is used. The following expression is

used to calculate the delay:

where DTL equals {1, 2, 3,..., 255}.

A zero value for DTL[7:0] causes a delay-after-transfer value of 8192/fsys.

Adequate delay between transfers must be specified for long data streams because

the QSPI requires time to load a transmit RAM entry for transfer. Receiving devices

need at least the standard delay between successive transfers. If the system clock is

operating at a slower rate, the delay between transfers must be increased proportion-

ately.

Table 9-3 Bits Per Transfer

BITS[3:0]

Bits Per Transfer

0000

0001

Reserved

0010

Reserved

0011

Reserved

0100

Reserved

0101

Reserved

0110

Reserved

0111

Reserved

1000

1001

1010

1011

1100

1101

1110

1111

Delay after Transfer

DTL[7:0]

sys

------------------------------------

if DT = 1

Standard Delay after Transfer

sys

---------

if DT = 0

Freescale Semiconductor, Inc.

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