SPMCK16Z4MPV16 datasheet(231/500 Pages) FREESCALE

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M68HC16 Z SERIES

QUEUED SERIAL MODULE

USER’S MANUAL

9-21

The QSPI transmits as many bits as it receives at each queue address, until the

BITS[3:0] value is reached or SS is negated. SS does not need to go high between

transfers as the QSPI transfers data until reaching the end of the queue, whether SS

remains low or is toggled between transfers.

When the QSPI reaches the end of the queue, it sets the SPIF flag. If the SPIFIE bit

in SPCR2 is set, an interrupt request is generated when SPIF is asserted. At this point,

the QSPI clears SPE and stops unless wrap-around mode is enabled.

9.3.5.4 Slave Wrap-Around Mode

Slave wrap-around mode is enabled by setting the WREN bit in SPCR2. The queue

can wrap to pointer address $0 or to the address pointed to by NEWQP, depending on

the state of the WRTO bit in SPCR2. Slave wrap-around operation is identical to mas-

ter wrap-around operation.

9.3.6 Peripheral Chip Selects

Peripheral chip-select signals are used to select an external device for serial data

transfer. Chip-select signals are asserted when a command in the queue is executed.

Signals are asserted at a logic level corresponding to the value of the PCS[3:0] bits in

each command byte. More than one chip-select signal can be asserted at a time, and

more than one external device can be connected to each PCS pin, provided proper

fanout is observed. PCS0 shares a pin with the slave select (SS) signal, which initiates

slave mode serial transfer. If SS is taken low when the QSPI is in master mode, a

mode fault occurs.

To configure a peripheral chip-select, set the appropriate bit in PQSPAR, then config-

ure the chip-select pin as an output by setting the appropriate bit in DDRQS. The value

of the bit in PORTQS that corresponds to the chip-select pin determines the base state

of the chip-select signal. If base state is zero, chip-select assertion must be active high

(PCS bit in command RAM must be set); if base state is one, assertion must be active

low (PCS bit in command RAM must be cleared). PORTQS bits are cleared during re-

set. If no new data is written to PORTQS before pin assignment and configuration as

an output, the base state of chip-select signals is zero and chip-select pins should thus

be driven active-high.

9.4 Serial Communication Interface

The serial communication interface (SCI) communicates with external devices through

an asynchronous serial bus. The SCI uses a standard non-return to zero (NRZ) trans-

mission format. The SCI is fully compatible with other Freescale SCI systems, such as

those on M68HC11 and M68HC05 devices. Figure 9-10 is a block diagram of the SCI

transmitter. Figure 9-11 is a block diagram of the SCI receiver.

Freescale Semiconductor, Inc.

For More Information On This Product,

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SPMCK16Z4MPV16 Datasheet(PDF) 231 Page - Freescale Semiconductor, Inc

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