WM1811A datasheet(31/328 Pages) WOLFSON

Part #	WM1811A

Description	Multi-Channel Audio Hub CODEC for Smartphones

PDF	328 Pages

Scroll/Zoom	100%

Manufacturer	WOLFSON [Wolfson Microelectronics plc]

Direct Link	http://www.wolfsonmicro.com

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31 / 328 page

Production Data

WM1811A

PD, November 2013, Rev 4.1

SIGNAL TIMING REQUIREMENTS

SYSTEM CLOCKS & FREQUENCY LOCKED LOOP (FLL)

Figure 1 Master Clock Timing

Test Conditions

The following timing information is valid across the full range of recommended operating conditions.

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNIT

Master Clock Timing (MCLK1 and MCLK2)

MCLK cycle time

TMCLKY

MCLK as input to FLL,

FLLn_REFCLK_DIV = 10, 11

MCLK as input to FLL,

FLLn_REFCLK_DIV = 01

MCLK as input to FLL,

FLLn_REFCLK_DIV = 00

FLL not used, AIFnCLK_DIV = 1

FLL not used, AIFnCLK_DIV = 0

MCLK duty cycle

(= TMCLKH : TMCLKL)

60:40

40:60

Frequency Locked Loops (FLL1 and FLL2)

FLL Input Frequency

FLLn_REFCLK_DIV = 00

0.032

13.5

MHz

FLLn_REFCLK_DIV = 01

0.064

FLLn_REFCLK_DIV = 10

0.128

FLLn_REFCLK_DIV = 11

0.256

Internal Clocking

AIF1CLK frequency

12.5

MHz

AIF2CLK frequency

12.5

MHz

SYSCLK frequency

12.5

MHz

WM1811A Datasheet(PDF) 31 Page - Wolfson Microelectronics plc

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