AT89LP51RB2 datasheet(73/254 Pages) ATMEL

73 / 254 page

3722A–MICRO–10/11

AT89LP51RB2/RC2/IC2 Preliminary

Digital inputs on P2.4, P2.5, P2.6 and P2.7 are disabled whenever an analog comparator is

enabled by setting the CENA or CENB bits in ACSRA and ACSRB and that pin is configured for

input-only mode. To use an analog input pin as a high-impedance digital input while a compara-

tor is enabled, that pin should be configured in open-drain mode and the corresponding port

Digital inputs on Port 0 are disabled for each pin configured for input-only mode whenever the

ADC is enabled by setting the ADCE bit and clearing the DAC bit in DADC. To use any Port 0

input pin as a high-impedance digital input while the ADC is enabled, that pin should be config-

ured in open-drain mode and the corresponding port register bit should be set to 1. When DAC

mode is enabled, P2.2 and P2.3 are forced to input-only mode.

12.3

Port Read-Modify-Write

A read from a port will read either the state of the pins or the state of the port register depending

on which instruction is used. Simple read instructions will always access the port pins directly.

Read-modify-write instructions, which read a value, possibly modify it, and then write it back, will

always access the port register. This includes bit write instructions such as CLR or SETB as they

actually read the entire port, modify a single bit, then write the data back to the entire port. See

Table 12-5 for a complete list of Read-Modify-Write instruction which may access the ports.

12.4

Port Alternate Functions

Most general-purpose digital I/O pins of the AT89LP51RB2/RC2/IC2 share functionality with the

various I/Os needed for the peripheral units. Table 12-7 lists the alternate functions of the port

pins. Alternate functions are connected to the pins in a logic AND fashion. In order to enable the

alternate function on a port pin, that pin must have a “1” in its corresponding port register bit,

otherwise the input/output will always be “0”. However, alternate functions may be temporarily

forced to “0” by clearing the associated port bit, provided that the pin is not in input-only mode.

Furthermore, each pin must be configured for the correct input/output mode as required by its

peripheral before it may be used as such. Table 12-6 shows how to configure a generic pin for

use with an alternate function. If two or more port pins on the same 8-bit require difference direc-

tions, the port must be configured for bidirectional operation.

Table 12-5.

Port Read-Modify-Write Instructions

Mnemonic

Instruction

Example

ANL

Logical AND

ANL P1, A

ORL

Logical OR

ORL P1, A

XRL

Logical EX-OR

XRL P1, A

JBC

Jump if bit set and clear bit

JBC P3.0, LABEL

CPL

Complement bit

CPL P3.1

INC

Increment

INC P1

DEC

Decrement

DEC P3

DJNZ

Decrement and jump if not zero

DJNZ P3, LABEL

MOV PX.Y, C

Move carry to bit Y of Port X

MOV P1.0, C

CLR PX.Y

Clear bit Y of Port X

CLR P1.1

SETB PX.Y

Set bit Y of Port X

SETB P3.2

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