AT89LP51RB2 datasheet(35/254 Pages) ATMEL

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3722A–MICRO–10/11

AT89LP51RB2/RC2/IC2 Preliminary

5.4

Enhanced Dual Data Pointers

The AT89LP51RB2/RC2/IC2 provides two 16-bit data pointers: DPTR0 and DPTR1. The data

pointers are used by several instructions to access the program or data memories. The

Auxiliary 1 Register (AUXR1) and Data Pointer Configuration Register (DPCF) control operation

of the dual data pointers (see Table 5-6 on page 37 and Table 5-7 on page 37). The DPS bit in

AUXR1 selects which data pointer is currently referenced by instructions including the DPTR

operand. Each data pointer may also be accessed at a pair of SFR addresses that also depend

on the DPS value. The data pointer referenced by DPS is located at the register pair DPL and

DPH (82H an 83H), and the alternate data pointer not referenced by DPS is located at the regis-

ter pair DPLB and DPHB (D4H and D5H). When DPS is toggled, the two data pointers also swap

which SFR pair will access them as shown in Table 5-2. The AT89LP51RB2/RC2/IC2 provides

two methods for fast context switching of the data pointers:

• Bit 2 of AUXR1 is hard-wired as a logic 0. The DPS bit may be toggled (to switch data

pointers) simply by incrementing the AUXR1 register, without altering other bits in the register

unintentionally. This is the preferred method when only a single data pointer will be used at

one time.

EX:

INC

AUXR1

; Toggle DPS

•In some cases, both data pointers must be used simultaneously. To prevent frequent toggling

of DPS, the AT89LP51RB2/RC2/IC2 supports a prefix notation for selecting the opposite data

pointer per instruction. All DPTR instructions, with the exception of JMP @A+DPTR, when

prefixed with an 0A5H opcode will use the inverse value of DPS (DPS) to select the data

pointer. Some assemblers may support this operation by using the /DPTR operand. For

example, the following code performs a block copy within EDATA:

MOV

AUXR1, #00H

; DPS = 0

MOV

DPTR, #SRC

; load source address to dptr0

MOV

/DPTR, #DST

; load destination address to dptr1

MOV

R7, #BLKSIZE

; number of bytes to copy

COPY:

MOVX A, @DPTR

; read source (dptr0)

INC

DPTR

; next src (dptr0+1)

MOVX @/DPTR, A

; write destination (dptr1)

INC

/DPTR

; next dst (dptr1+1)

DJNZ R7, COPY

For assemblers that do not support this notation, the 0A5H prefix must be declared in-line:

EX:

0A5H

INC

DPTR

; equivalent to INC /DPTR

Table 5-2.

Data Pointer Register Access

SFR

DPS = 0

DPS = 1

DPL (82H)

DP0L

DP1L

DPH (83H)

DP0H

DP1H

DPLB (D4H)

DP1L

DP0L

DPHB (D5H)

DP1H

DP0H

AT89LP51RB2 Datasheet(PDF) 35 Page - ATMEL Corporation

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