AT89LP51RB2 datasheet(9/254 Pages) ATMEL

9 / 254 page

3722A–MICRO–10/11

AT89LP51RB2/RC2/IC2 Preliminary

2.2.2

Software Options

Table 2-2 lists some important software configuration bits that affect operation at the system

level. These can be changed by the application software but are set to their default values upon

any reset. Most peripherals also have multiple configuration bits that are not listed here.

Table 2-1.

User Configuration Fuses

Fuse Name

Description

Clock Source A

Selects between the High Speed Crystal Oscillator, Low Power

Crystal Oscillator, External Clock on XTAL1A or Internal RC Oscillator

for the source of the system clock when oscillator A is selected.

Clock Source B

Selects between the 32 kHz Crystal Oscillator, External Clock on

XTAL1B or Internal RC Oscillator for the source of the system clock

when oscillator B is selected (AT89LP51IC2 Only).

Oscillator Select

Selects whether oscillator A or B is enabled to boot the device.

(AT89LP51IC2 Only)

X2 Mode

Selects the default state of whether the clock source is divided by two

(X1) or not (X2) to generate the system clock.

Start-up Time

Selects time-out delay for the POR/BOD/PWD wake-up period.

Compatibility Mode

Configures the CPU in 12-clock compatibility or single-cycle fast

execution mode.

XRAM Configuration

Configures if access to on-chip memories that are mapped to the

external data memory address space is enabled/disabled by default.

Bootloader Jump Bit

Enables or disables the on-ship bootloader.

On-Chip Debug Enable

Enables or disables On-Chip Debug. OCD must be enabled prior to

using an in-circuit debugger with the device.

In-System Programming Enable

Enables or disables In-System Programming.

User Signature Programming Enable

Enables or disables programming of User Signature array.

Default Port State

Configures the default port state as input-only mode (tristated) or

quasi-bidirectional mode (weakly pulled high).

Low Power Mode

Enables or disables power reduction features for lower system

frequencies.

Table 2-2.

Important Software Configuration Bits

Bit(s)

SFR Location

Description

PxM0.y

PxM1.y

P0M0, P0M1, P1M0, P1M1,

P2M0, P2M1, P3M0, P3M1,

P4M0, P4M1

Configures the I/O mode of Port x Pin y to be one of input-only, quasi-

bidirectional, push-pull output or open-drain. The default state is

controlled by the Default Port State fuse above

CKRL

Selects the division ratio between the oscillator and the system clock

TPS

3-0

CLKREG.7-4

Selects the division ratio between the system clock and the timers

ALES

AUXR.0

Enables/disables toggling of ALE

EXRAM

AUXR.1

Enables/disables access to on-chip memories that are mapped to the

external data memory address space

1-0

AUXR.6-5

Selects the number of wait states when accessing external data

memory

XSTK

AUXR1.4

Configures the hardware stack to be in RAM or extra RAM

ENBOOT

AUXR1.5

Enables/disables access to the on-chip Flash API

AT89LP51RB2 Datasheet(PDF) 9 Page - ATMEL Corporation

AT89LP51RB2 Datasheet(HTML) 9 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL