AT89LP51RB2 datasheet(47/254 Pages) ATMEL

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3722A–MICRO–10/11

AT89LP51RB2/RC2/IC2 Preliminary

6.8

System Clock Prescaler

The AT89LP51RB2/RC2/IC2 includes an 8-bit prescaler that allows the system clock to be

divided down from the selected clock source by even numbers in the range 4–1020 in X1 mode

and 2–510 in X2 mode. The prescaler can reduce power consumption by decreasing the opera-

tional frequency during non-critical periods. The prescaler is implemented as an 8-bit counter

with reload. Upon overflow from FFH to 00H the counter is reloaded with the value of the CKRL

by the following equations where f

OSC is the frequency of the selected clock source and X2 is the

value of CKCON0.0:

The clock divider will prescale the clock for the CPU and all peripherals. The value of CKRL may

be changed at any time without interrupting normal execution. Changes to CKRL will take affect

on the next prescaler overflow. When CKRL is updated, the new frequency will take affect within

a maximum period of 1024 x t

OSC. The prescaler is disabled by reset.

fSYS

fOSC

255

CKRL

–

()

-----------------------------------------------

CKRL

255

()

SYS

OSC

----------------------------

CKRL

255

()

Table 6-7.

CKRL

– Clock Reload Register

CKRL = 97H

Reset Value = 1111 1111B

Not Bit Addressable

CKRL7

CKRL6

CKRL5

CKRL4

CKRL3

CKRL2

CKRL1

CKRL0

Bit

543

Symbol

Function

CKRL7-0

Clock Reload. CKRL holds the reload value for the 8-bit system clock prescaler. When CKRL = FFH the prescaler is

disabled and no division is used. For all other values, the prescaler counts up to FFH and is reloaded with the value of

CKRL on the overflow to 00H. Each overflow of the prescaler will toggle the system clock. Changes to CKRL will take

affect on the next overflow.

Table 6-8.

CLKREG

– Clock Register

CLKREG = AEH

Reset Value = 0101 XXXXB

Not Bit Addressable

TPS3TPS2TPS1TPS0

———

—

Bit

543

Symbol

Function

TPS3-0

Timer Prescaler. The Timer Prescaler selects the time base for Timer 0, Timer 1, Timer 2, PCA and the Watchdog

Timer. The prescaler is implemented as a 4-bit binary down counter. When the counter reaches zero it is reloaded with

the value stored in the TPS bits to give a division ratio between 1 and 16. By default TPS is set to 5 for counting every six

cycles (AT89C51RB2/RC2/IC2 compatibility). The prescaler is always enabled in Compatibility mode. In Fast mode the

prescaler is off by default and can be individually enabled for the peripherals through the CKCON0 and CKCON1 SFRs.

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