AT89LP51RB2 datasheet(55/254 Pages) ATMEL

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3722A–MICRO–10/11

AT89LP51RB2/RC2/IC2 Preliminary

Power Saving Modes

The AT89LP51RB2/RC2/IC2 supports two different software selectable power-reducing modes:

Idle and Power-down. These modes are accessed through the PCON register. Additional steps

may be required to achieve the lowest possible power consumption while using these modes. In

addition the AT89LP51RB2/RC2/IC2 has fusible configuration options that can further reduce

the active power consumption under certain circumstances.

8.1

Idle Mode

Setting the IDL bit in PCON enters idle mode. Idle mode halts the internal CPU clock. The CPU

state is preserved in its entirety, including the RAM, stack pointer, program counter, program

status word, and accumulator. The Port pins hold the logic states they had at the time that Idle

was activated. Idle mode leaves the peripherals running in order to allow them to wake up the

CPU when an interrupt is generated. The timer and UART peripherals continue to function dur-

ing Idle. If these functions are not needed during idle, they should be explicitly disabled by

clearing the appropriate control bits in their respective SFRs. The watchdog may be selectively

enabled or disabled during Idle by setting/clearing the WDIDLE bit. The Brown-out Detector is

always active during Idle. Any enabled interrupt source or reset may terminate Idle mode. When

exiting Idle mode with an interrupt, the interrupt will immediately be serviced, and following RETI

the next instruction to be executed will be the one following the instruction that put the device

into Idle.

The power consumption during Idle mode can be further reduced by prescaling down the system

clock using the System Clock Prescaler (Section 6.8 on page 47). Be aware that the clock

divider will affect all peripheral functions and baud rates may need to be adjusted to maintain

their rate with the new clock frequency.

Table 8-1.

PCON

– Power Control Register

PCON = 87H

Reset Value = 000X 0000B

Not Bit Addressable

SMOD1

SMOD0

PWDEX

POF

GF1

GF0

IDL

Bit

543

Symbol

Function

SMOD1

Double Baud Rate bit. Doubles the baud rate of the UART in Modes 1, 2, or 3.

SMOD0

Frame Error Select. When SMOD0 = 1, SCON.7 is SM0. When SMOD0 = 1, SCON.7 is FE. Note that FE will be set after

a frame error regardless of the state of SMOD0.

PWDEX

Power-down Exit Mode. When PWDEX = 0, wake up from Power-down is externally controlled. When PWDEX = 1, wake

up from Power-down is internally timed.

POF

Power Off Flag. POF is set to “1” during power up (i.e. cold reset). It can be set or reset under software control and is not

affected by RST or BOD (i.e. warm resets).

GF1, GF0

General-purpose Flags

Power-down bit. Setting this bit activates power-down operation. The PD bit is cleared automatically by hardware when

waking up from power-down.

IDL

Idle Mode bit. Setting this bit activates Idle mode operation. The IDL bit is cleared automatically by hardware when

waking up from idle

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