AT89LP51RB2 datasheet(78/254 Pages) ATMEL

78 / 254 page

3722A–MICRO–10/11

AT89LP51RB2/RC2/IC2 Preliminary

13.1

Registers

Table 13-1 lists the registers used by Timer 0/1. TCON, TCONB and TMOD are detailed below.

Note:

The RHn/RLn registers are not required by the Timer during Modes 0, 2 or 3 and may be used as

temporary storage registers in these modes, except when using the PWM generator.

Table 13-1.

Timer 0/1 Register Summary

Name

Address

Purpose

Bit-Addressable

TCON

88H

Control

TMOD

89H

Mode

TL0

8AH

Timer 0 low-byte

TL1

8BH

Timer 1 low-byte

TH0

8CH

Timer 0 high-byte

TH1

8DH

Timer 1 high-byte

TCONB

91H

Mode

RL0

F2H

Timer 0 reload low-byte

RL1

F3H

Timer 1 reload low-byte

RH0

F4H

Timer 0 reload high-byte

RH1

F5H

Timer 1 reload high-byte

Table 13-2.

TCON

– Timer/Counter Control Register

TCON = 88H

Reset Value = 0000 0000B

Bit Addressable

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

Bit

543

Symbol

Function

TF1

Timer 1 Overflow Flag

Set by hardware on Timer/Counter overflow. Cleared by hardware when the processor vectors to interrupt routine.

TR1

Timer 1 Run Control

Set/cleared by software to turn Timer/Counter on/off.

TF0

Timer 0 Overflow Flag

Set by hardware on Timer/Counter overflow. Cleared by hardware when the processor vectors to interrupt routine.

TR0

Timer 0 Run Control

Set/cleared by software to turn Timer/Counter on/off.

IE1

Interrupt 1 Edge Flag

Set by hardware when external interrupt edge detected. Cleared when interrupt processed.

IT1

Interrupt 1 Type

Set/cleared by software to specify falling edge/low level triggered external interrupts.

IE0

Interrupt 0 Edge Flag

Set by hardware when external interrupt edge detected. Cleared when interrupt processed.

IT0

Interrupt 0 Type

Set/cleared by software to specify falling edge/low level triggered external interrupts.

AT89LP51RB2 Datasheet(PDF) 78 Page - ATMEL Corporation

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