AT89LP51RB2 datasheet(46/254 Pages) ATMEL

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3722A–MICRO–10/11

AT89LP51RB2/RC2/IC2 Preliminary

6.6.4

Registers

6.7

X1/X2 Feature

The AT89LP51RB2/RC2/IC2 includes the X1/X2 feature for compatibility with the existing

AT89C51RB2/RC2/IC2. This feature allows a divider-by-2 to be switched in/out between the

oscillator source and the main system clock. This feature is controlled by the X2 bit in CKCON0

(See Table 6-9 on page 48). When X2 = 0 the system clock is divided by two from the oscillator

source, ensuring a 50% duty cycle regardless of the cyclic ratio at the oscillator output. When

X2 = 1 the oscillator output is passed through with no division. In this case the duty cycle at the

oscillator must be between 40% and 60%. Note that the naming convention can be confusing

since X1 means divide-by-2 and X2 means divide-by-1 as shown in Table 6-7. The default state

of the X2 bit is set by the X2 User fuse (See Section 24.2 on page 188) but can always be

changed by software. This fuse is also shadowed in the X2 bit of the bootloader Hardware Secu-

rity Byte (HSB). Note that the fuse/HSB bit is inverted from the control bit in the CKCON0 SFR.

Table 6-4.

CKSEL

– Clock Selection Register

CKSEL = 85H (AT89LP51IC2 Only)

Reset Value = XXXX XXX?B

Not Bit Addressable

––

–––

––

CKS

Bit

543

Symbol

Function

CKS

Clock Select. Clear CKS to connect the system clock (CPU and peripherals) to the OSCB source. Set CKS to connect

the system clock to the OSCA source. The default state is set by the Oscillator Select user fuse. See Section 24.2 on

page 188.

Table 6-5.

OSCCON

– Oscillator Control Register

OSCCON = 86H (AT89LP51IC2 Only)

Reset Value = XXXX X0??B

Not Bit Addressable

––

–––

SCLKT0

OscBEn

OscAEn

Bit

543

Symbol

Function

SCLKT0

Sub Clock Timer 0. Clear to connect the Timer 0 counter input to T0 (P3.4). Set to connect the Timer 0 counter input to

OSCB output divided by 128. OSCB must be sourced from crystal oscillator B to use this feature.

OscBEn

OSCB Enable. Clear to power down the OSCB source. Set to enable the OSCB source. The default state is set by the

Oscillator Select user fuse. See Section 24.2 on page 188. OscBEn cannot be disabled when CKS =0. Disabling OSCB

will free the XTAL1B and XTAL2B pins for use as P1.0 and P4.2.

OscAEn

OSCA Enable. Clear to power down the OSCA source. Set to enable the OSCA source. The default state is set by the

Oscillator Select user fuse. See Section 24.2 on page 188. OscAEn cannot be disabled when CKS =1.

Table 6-6.

X1/X2 Modes

Mode

(CKCON0.0)

CPU Clock

XTAL1

Duty Cycle

X2 Fuse

(HSB.X2)

fCPU = fSYS/2

No limits

FFH (1)

fCPU = fSYS/1

40–60%

00H (0)

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