AT89LP51RB2 datasheet(14/254 Pages) ATMEL

14 / 254 page

3722A–MICRO–10/11

AT89LP51RB2/RC2/IC2 Preliminary

Figure 3-1.

Program Memory Map

3.1.1

External Program Memory

The AT89LP51RB2/RC2/IC2 implements 24/32/32 KB of the program memory space internally.

The AT89LP51RB2/RC2/IC2 does not support forcing external execution using the EA pin; how-

ever it does allow for up to 40/32/32 KB of external program memory to be mapped into the

upper portions of the address space. For AT89LP51RB2 addresses 6000H–FFFFH are mapped

to external program memory. For AT89LP51RC2/IC2 addresses 8000H–FFFFH are mapped to

external program memory.

The AT89LP51RB2/RC2/IC2 uses the standard 8051 external program memory interface with

the upper address on Port 2, the lower address and data in/out multiplexed on Port 0, and the

ALE and PSEN strobes. Program memory addresses are always 16-bits wide. External program

execution sacrifices two full 8-bit ports, P0 and P2, to the function of addressing the program

memory.

Figure 3-2 shows a hardware configuration for accessing up to 64K bytes of external ROM using

a 16-bit linear address. Port 0 serves as a multiplexed address/data bus to the ROM. The

Address Latch Enable strobe (ALE) is used to latch the lower address byte into an external reg-

ister so that Port 0 can be freed for data input/output. Port 2 provides the upper address byte

throughout the operation. PSEN strobes the external memory.

Figure 3-3 shows the timing of the external program memory interface. ALE is emitted at a con-

stant rate of 1/3 of the system clock with a 1/3 duty cycle. PSEN is emitted at a similar rate, but

with 50% duty cycle. The new address changes in the middle of the ALE pulse for latching on

the falling edge and is tristated at the falling edge of PSEN. The instruction data is sampled from

P0 and latched internally during the high phase of the clock prior to the rising edge of PSEN.

This timing applies to both Compatibility and Fast modes. In Compatibility mode there is no dif-

ference in instruction timing between internal and external execution.

0000

FFFF

0000

007F

User Signature Array

0100

01FF

Atmel Signature Array

SIGEN=0

SIGEN=1

8000

7FFF

External Program

Memory

(XCODE: 30KB)

Internal Program

Memory

(CODE: 32KB)

0000

FFFF

0000

007F

User Signature Array

0100

01FF

Atmel Signature Array

AT89LP51RB2

ENBOOT = 1

F800

F7FF

Boot ROM

(BOOT: 2KB)

0000

FFFF

0000

007F

User Signature Array

0100

01FF

Atmel Signature Array

AT89LP51RB2

ENBOOT = 0

0000

FFFF

0000

007F

User Signature Array

0100

01FF

Atmel Signature Array

8000

7FFF

External Program

Memory

(XCODE: 32KB)

Internal Program

Memory

(CODE: 32KB)

AT89LP51RC2/IC2

ENBOOT = 1

AT89LP51RC2/IC2

ENBOOT = 0

F800

F7FF

Boot ROM

(BOOT: 2KB)

6000

5FFF

External Program

Memory

(XCODE: 40KB)

Internal Program

Memory

(CODE: 24KB)

6000

5FFF

External Program

Memory

(XCODE: 38KB)

Internal Program

Memory

(CODE: 24KB)

AT89LP51RB2 Datasheet(PDF) 14 Page - ATMEL Corporation

AT89LP51RB2 Datasheet(HTML) 14 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL