AT89LP51RB2 datasheet(34/254 Pages) ATMEL

34 / 254 page

3722A–MICRO–10/11

AT89LP51RB2/RC2/IC2 Preliminary

Figure 5-4.

M Register with Sliding Window

As a consequence of the MAC unit, the standard 8x8 MUL AB instruction can support signed

multiplication. The SMLA and SMLB bits in DSPR control the multiplier’s interpretation of the

ACC and B registers, allowing any combination of signed and unsigned operand multiplication.

These bits have no effect on the MAC operation which always multiplies signed-by-signed.

23 – 16

15 – 8

7 – 0

31 – 24

39 – 32

Byte 4

Byte 3

Byte 2

Byte 1

Byte 0

MACH

MACL

MACH

MACL

MACH

MACL

MACH

MACL

MRW1-0 = 00B

MRW1-0 = 01B

MRW1-0 = 10B

MRW1-0 = 11B

Table 5-1.

DSPR

– Digital Signal Processing Configuration Register

DSPR = E2H

Reset Value = 0000 0000B

Not Bit Addressable

MRW1

MRW0

SMLB

SMLA

CBE1

CBE0

MVCD

DPRB

Bit

543

Symbol

Function

MRW1-0

M Register Window. Selects which pair of bytes from the 5-byte M register is accessible through MACH (E5H) and

MACL (E4H) as shown in Figure 5-4. For example, MRW = 10B for normal 16-bit fixed-point operations where the lowest

order portion of the fractional result is discarded.

SMLB

Signed Multiply Operand B. When SMLB = 0, the MUL AB instruction treats the contents of B as an unsigned value.

When SMLB = 1, the MUL AB instruction interprets the contents of B as a signed two’s complement value. SMLB does

not affect the MAC operation.

SMLA

Signed Multiply Operand A. When SMLA = 0, the MUL AB instruction treats the contents of ACC as an unsigned value.

When SMLA = 1, the MUL AB instruction interprets the contents of ACC as a signed two’s complement value. SMLA

does not affect the MAC operation.

CBE1

DPTR1 Circular Buffer Enable. Set CBE1 = 1 to configure DPTR1 for circular addressing over the two circular buffer

address ranges. Clear CBE1 for normal DPTR operation.

CBE0

DPTR0 Circular Buffer Enable. Set CBE0 = 1 to configure DPTR0 for circular addressing over the two circular buffer

address ranges. Clear CBE0 for normal DPTR operation.

MVCD

MOVC Index Disable. When MVCD = 0, the MOVC A, @A+DPTR instruction functions normally with indexed

addressing. Setting MVCD = 1 disables the indexed addressing mode such that MOVC A, @A+DPTR functions as

MOVC A, @DPTR.

DPRB

DPTR1 Redirect to B. DPRB selects the source/destination register for MOVC/MOVX instructions that reference DPTR1.

When DPRB = 0, ACC is the source/destination. When DPRB = 1, B is the source/destination. DPRB does not change

the index register for MOVC instructions.

AT89LP51RB2 Datasheet(PDF) 34 Page - ATMEL Corporation

AT89LP51RB2 Datasheet(HTML) 34 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL