AT89LP51RB2 datasheet(104/254 Pages) ATMEL

104 / 254 page

104

3722A–MICRO–10/11

AT89LP51RB2/RC2/IC2 Preliminary

15.7

PCA Watchdog Timer

An on-board watchdog timer is available with the PCA to improve the reliability of the system

without increasing chip count. Watchdog timers are useful for systems that are susceptible to

noise, power glitches, or electrostatic discharge. Module 4 is the only PCA module that can be

programmed as a watchdog. However, this module can still be used for other modes if the

watchdog is not needed. Figure 15-4 shows a diagram of how the watchdog works. The user

pre-loads a 16-bit value in the compare registers. Just like the other compare modes, this 16-bit

value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be

generated. This reset will not cause the RST pin to be driven active.

In order to hold off the reset, the user has three options:

Periodically change the compare value so it will never match the PCA timer.

Periodically change the PCA timer value so it will never match the compare values.

Disable the watchdog by clearing the WDTE bit before a match occurs and then re-

enable it.

The first two options are more reliable because the watchdog timer is never disabled as in option

#3. If the program counter ever goes astray, a match will eventually occur and cause an internal

reset. The second option is also not recommended if other PCA modules are being used.

Remember, the PCA timer is the time base for all modules; changing the time base for other

modules would not be a good idea. Thus, in most applications the first solution is the best option.

This watchdog timer won’t generate a reset out on the reset pin. Only the Hardware Watchdog

can generate a board-level reset.

16. Hardware Watchdog Timer

The programmable Hardware Watchdog Timer (WDT) protects the system from incorrect execu-

tion by triggering a system reset when it times out after the software has failed to feed the timer

prior to the timer overflow. Each WDT clock cycle depends on the Timer Prescaler (see Section

6.9 on page 48). By Default the WDT counts every 6 CPU clock cycles since TPS = 5. The pres-

caler bits, PS0, PS1 and PS2 in SFR WDTPRG are used to set the period of the Watchdog

Timer from 16K to 2048K WDT clock cycles. The WDT is disabled by Reset and during Power-

down mode. When the WDT times out without being serviced, a RST pulse last 96 system

clocks (48 system clocks in X2 Mode) is generated to reset the CPU. This reset is also driven

out on the RST pin (see Section 7.4 on page 54) if the DISRTO bit in WDTPRG is not set. See

Table 16-1 for the available WDT period selections

The Watchdog Timer consists of a 14-bit timer with 7-bit programmable prescaler. Writing the

sequence 1EH/E1H to the WDTRST register enables the timer. When the WDT is enabled, the

WDTEN bit in WDTPRG will be set to “1”. To prevent the WDT from generating a reset when if

overflows, the watchdog feed sequence must be written to WDTRST before the end of the time-

out period. To feed the watchdog, two write instructions must be sequentially executed success-

fully. Between the two write instructions, SFR reads are allowed, but writes are not allowed. The

instructions should move 1EH to the WDTRST register and then 1EH to the WDTRST register.

An incorrect feed or enable sequence will cause an immediate watchdog reset.

Time-out Period

WTO

()

fSYS

-----------------------------

TPS

()

AT89LP51RB2 Datasheet(PDF) 104 Page - ATMEL Corporation

AT89LP51RB2 Datasheet(HTML) 104 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL