PIC16C765SLASHP datasheet(29/158 Pages) MICROCHIP

29 / 158 page

Advanced Information

DS41124A-page 29

PIC16C745/765

4.3

PCL and PCLATH

The program counter (PC) is 13-bits wide. The low byte

comes from the PCL register, which is a readable and

writable register. The upper bits (PC<12:8>) are not

readable, but are indirectly writable through the

PCLATH register. On any reset, the upper bits of the PC

will be cleared. Figure 4-3 shows the two situations for

the loading of the PC. The upper example in the figure

shows how the PC is loaded on a write to PCL

(PCLATH<4:0>

→ PCH). The lower example in the fig-

ure shows how the PC is loaded during a CALL or GOTO

instruction (PCLATH<4:3>

→ PCH).

FIGURE 4-3:

LOADING OF PC IN

DIFFERENT SITUATIONS

4.3.1

COMPUTED GOTO

A computed GOTO is accomplished by adding an offset

to the program counter (ADDWF PCL). When doing a

table read using a computed GOTO method, care

should be exercised if the table location crosses a PCL

memory boundary (each 256 byte block). Refer to the

application note

“Implementing a Table Read" (AN556).

4.3.2

STACK

The PIC16CXX family has an 8-level deep x 13-bit wide

hardware stack. The stack space is not part of either

program or data space and the stack pointer is not

readable or writable. The PC is PUSHed onto the stack

when a CALL instruction is executed or an interrupt

causes a branch. The stack is POPed in the event of a

RETURN,RETLW

or a RETFIE instruction execution.

PCLATH is not affected by a PUSH or POP operation.

The stack operates as a circular buffer. This means that

after the stack has been PUSHed eight times, the ninth

push overwrites the value that was stored from the first

push. The tenth push overwrites the second push (and

so on).

4.4

Program Memory Paging

PIC16CXX devices are capable of addressing a contin-

uous 8K word block of program memory. The CALL and

GOTO

instructions provide only 11 bits of address to

allow branching within any 2K program memory page.

When doing a CALL or GOTO instruction, the upper 2

bits of the address are provided by PCLATH<4:3>.

When doing a CALL or GOTO instruction, the user must

ensure that the page select bits are programmed so

that the desired program memory page is addressed. If

a return from a CALL instruction (or interrupt) is exe-

cuted, the entire 13-bit PC is pushed onto the stack.

Therefore, manipulation of the PCLATH<4:3> bits is not

required for the return instructions (which POPs the

address from the stack).

Example 4-1 shows the calling of a subroutine in

page 1 of the program memory. This example assumes

that PCLATH is saved and restored by the interrupt ser-

vice routine (if interrupts are used).

EXAMPLE 4-1:

CALL OF A SUBROUTINE IN

PAGE 1 FROM PAGE 0

ORG

0x500

BSF

PCLATH,3

;Select page 1 (800h-FFFh)

CALL SUB1_P1

;Call subroutine in

;page 1 (800h-FFFh)

ORG

0x900

;page 1 (800h-FFFh)

SUB1_P1

;called subroutine

;page 1 (800h-FFFh)

RETURN

;return to Call subroutine

;in page 0 (000h-7FFh)

PCLATH<4:0>

PCLATH

Instruction with

ALU

GOTO,CALL

Opcode <10:0>

11 10

PCLATH<4:3>

PCH

PCL

PCLATH

PCH

PCL

PCL as

Destination

Note 1: There are no status bits to indicate stack

overflow or stack underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions that

occur from the execution of the CALL,

RETURN,

RETLW,

and RETFIE instruc-

tions, or the vectoring to an interrupt

address.

PIC16C765/P Datasheet(PDF) 29 Page - Microchip Technology

PIC16C765/P Datasheet(HTML) 29 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL