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PIC16C765/P Datasheet(PDF) 18 Page - Microchip Technology |
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PIC16C765/P Datasheet(HTML) 18 Page - Microchip Technology |
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18 / 158 page  PIC16C745/765 DS41124A-page 18 Advanced Information © 1999 Microchip Technology Inc. Bank 1 80h INDF(3) Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 82h PCL(3) Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000 83h STATUS(3) IRP RP1 RP0 TO PD ZDC C 0001 1xxx 000q quuu 84h FSR(3) Indirect data memory address pointer xxxx xxxx uuuu uuuu 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 86h TRISB PORTB Data Direction Register 1111 1111 1111 1111 87h TRISC TRISC7 TRISC8 — — — TRISC2 TRISC1 TRISC0 11-- -111 11-- -111 88h TRISD(4) PORTD Data Direction Register 1111 1111 1111 1111 89h TRISE(4) IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111 8Ah PCLATH(1,3) — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 8Bh INTCON(3) GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 8Ch PIE1 PSPIE(4) ADIE RCIE TXIE USBIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 8Dh PIE2 — — — — — — —CCP2IE ---- ---0 ---- ---0 8Eh PCON — — — — — —POR BOR ---- --qq ---- --uu 8Fh — Unimplemented — — 90h — Unimplemented — — 91h — Unimplemented — — 92h PR2 Timer2 Period Register 1111 1111 1111 1111 93h — Unimplemented — — 94h — Unimplemented — — 95h — Unimplemented — — 96h — Unimplemented — — 97h — Unimplemented — — 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 9Ah — Unimplemented — — 9Bh — Unimplemented — — 9Ch — Unimplemented — — 9Dh — Unimplemented — — 9Eh — Unimplemented — — 9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000 TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (2) Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 3: These registers can be addressed from either bank. 4: The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745, always maintain these bits clear. |
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