PIC16C765SLASHP datasheet(52/158 Pages) MICROCHIP

52 / 158 page

PIC16C745/765

DS41124A-page 52

Advanced Information

CAPTURE/COMPARE/PWMN CONTROL REGISTER

(CCP1CON: 17H, CCP2CON: 1Dh)

R/W-0

—

DCnB1

DCnB0

CCPnM3

CCPnM2

CCPnM1 CCPnM0

R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7

bit0

bit 7-6:

Unimplemented: Read as ’0’

bit 5-4:

DCnB<1:0>: PWM Least Significant bits

Capture Mode: Unused

Compare Mode: Unused

PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRnL.

bit 3-0:

CCPnM<3:0>: CCPx Mode Select bits

0000

= Capture/Compare/PWM off (resets CCPn module)

0100

= Capture mode, every falling edge

0101

= Capture mode, every rising edge

0110

= Capture mode, every 4th rising edge

0111

= Capture mode, every 16th rising edge

1000

= Compare mode, set output on match (CCPnIF bit is set)

1001

= Compare mode, clear output on match (CCPnIF bit is set)

1010

= Compare mode, generate software interrupt on match (CCPnIF bit is set, CCPn pin is unaffected)

1011

= Compare mode, trigger special event (CCPnIF bit is set; CCPn resets TMR1or TMR3)

11xx

= PWM mode

PIC16C765/P Datasheet(PDF) 52 Page - Microchip Technology

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