PIC16C765SLASHP datasheet(92/158 Pages) MICROCHIP

92 / 158 page

PIC16C745/765

DS41124A-page 92

Advanced Information

12.1

A/D Acquisition Requirements

For the A/D converter to meet its specified accuracy,

the charge holding capacitor (CHOLD) must be allowed

to fully charge to the input channel voltage level. The

analog input model is shown in Figure 12-2. The

source impedance (RS) and the internal sampling

switch (RSS) impedance directly affect the time

required to charge the capacitor CHOLD. The sampling

switch (RSS) impedance varies over the device voltage

(VDD), Figure 12-2. The source impedance affects the

offset voltage at the analog input (due to pin leakage

current).

The maximum recommended impedance for ana-

log sources is 10 k

Ω. After the analog input channel is

selected (changed), the acquisition must pass before

the conversion can be started.

calculate

the

minimum

acquisition

time,

Equation 12-1 may be used. This equation assumes

that 1/2 LSb error is used (512 steps for the A/D). The

1/2 LSb error is the maximum error allowed for the A/D

to meet its specified resolution.

To calculate the minimum acquisition time, TACQ, see

the PICmicro™ Mid-Range MCU Family Reference

Manual (DS33023). In general, however, given a max

of 10k

Ω and a worst case temperature of 100°C, TACQ

will be no more than 16µsec.

FIGURE 12-2: ANALOG INPUT MODEL

EQUATION 12-1:

ACQUISITION TIME

CPIN

ANx

5 pF

VDD

VT = 0.6V

I leakage

RIC

≤ 1k

Sampling

Switch

SS RSS

CHOLD

= DAC capacitance

VSS

Sampling Switch

5 6 7 8 9 10 11

Ω)

VDD

= 51.2 pF

± 500 nA

Legend

CPIN

I leakage

RIC

CHOLD

= input capacitance

= threshold voltage

= leakage current at the pin due to

= interconnect resistance

= sampling switch

= sample/hold capacitance (from DAC)

various junctions

TACQ

Amplifier Settling Time +

Hold Capacitor Charging Time +

Temperature Coefficient

TAMP + TC + TCOFF

TAMP = 5

µS

TC = - (51.2pF)(1k

Ω + RSS + RS) In(1/511)

TCOFF = (Temp -25

°C)(0.05µS/°C)

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