PIC16C765SLASHP datasheet(99/158 Pages) MICROCHIP

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DS41124A-page 99

PIC16C745/765

13.4

Resets

13.4.1

POWER-ON RESET (POR)

A Power-on Reset pulse is generated on-chip when

VDD rise is detected (in the range of 1.5V - 2.1V). To

take advantage of the POR, just tie the MCLR pin

directly (or through a resistor) to VDD. This will elimi-

nate external RC components usually needed to create

a POR. A maximum rise time for VDD is specified. See

Electrical Specifications for details.

When the device starts normal operation (exits the

reset condition), device operating parameters (voltage,

frequency, temperature) must be met to ensure opera-

tion. If these conditions are not met, the device must be

held in reset until the operating conditions are met.

Brown-out reset may be used to meet the startup con-

ditions.

For additional information, refer to Application Note

AN607, “

Power-up Trouble Shooting.”

13.4.2

POWER-UP TIMER (PWRT)

The Power-up Timer provides a fixed 72 ms nominal

time-out on power-up from the POR. The PWRT oper-

ates on an internal RC oscillator. The device is kept in

reset as long as the PWRT is active. The PWRT’s time

delay allows VDD to rise to an acceptable level. A con-

figuration bit is provided to enable/disable the PWRT.

The power-up time delay will vary from chip to chip due

to VDD, temperature and process variation. See DC

parameters for details (TPWRT, parameter #33).

13.4.3

OSCILLATOR START-UP TIMER (OST)

The Oscillator Start-up Timer provides a delay of 1024

oscillator cycles (from OSC1 input) after the PWRT

delay. This ensures that the crystal oscillator or resona-

tor has started and stabilized.

The OST time-out is invoked only for HS mode and only

on power-on reset or wake-up from SLEEP.

13.4.4

BROWN-OUT RESET (BOR)

If VDD falls below VBOR (parameter D005) for longer

than TBOR (parameter #35), the brown-out situation

will reset the device. If VDD falls below VBOR for less

than TBOR, a reset may not occur.

Once the brown-out occurs, the device will remain in

brown-out reset until VDD rises above VBOR. The

power-up timer then keeps the device in reset for

TPWRT (parameter #33). If VDD should fall below VBOR

during TPWRT, the brown-out reset process will restart

when VDD rises above VBOR with the power-up timer

reset. Since the device is intended to operate at 5V

nominal only, the brown-out detect is always enabled

and the device will reset when Vdd falls below the

brown-out threshold. This device is unique in that the

•WDT timer will not activate after a brown-out if

PWRTE = 1 (inactive).

13.4.5

TIME-OUT SEQUENCE

On power-up, the time-out sequence is as follows: The

PWRT delay starts (if enabled) when a POR reset

occurs. Then OST starts counting 1024 oscillator

cycles when PWRT ends (HS). When the OST ends,

the device comes out of RESET.

If MCLR is kept low long enough, the time-outs will

expire. Bringing MCLR high will begin execution imme-

diately. This is useful for testing purposes or to synchro-

nize more than one PIC16CXX device operating in

parallel.

Table 13-5 shows the reset conditions for the STATUS,

PCON and PC registers, while Table 13-7 shows the

reset conditions for all the registers.

13.4.6

POWER CONTROL/STATUS REGISTER

(PCON)

The Brown-out Reset Status bit, BOR, is unknown on a

POR. It must be set by the user and checked on subse-

quent resets to see if bit BOR was cleared, indicating a

BOR occurred. The BOR bit is not predictable if the

brown-out reset circuitry is disabled.

The Power-on Reset Status bit, POR, is cleared on a

POR and unaffected otherwise. The user must set this

bit following a POR and check it on subsequent resets

to see if it has been cleared.

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