PIC16C765SLASHP datasheet(103/158 Pages) MICROCHIP

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Advanced Information

DS41124A-page 103

PIC16C745/765

13.6

Interrupts

The interrupt control register (INTCON) records individ-

ual interrupt requests in flag bits. It also has individual

and global interrupt enable bits.

A global interrupt enable bit, GIE (INTCON<7>)

enables (if set) all un-masked interrupts or disables (if

cleared) all interrupts. When bit GIE is enabled, and an

interrupt’s flag bit and mask bit are set, the interrupt will

vector immediately. Individual interrupts can be dis-

abled through their corresponding enable bits in vari-

ous

registers.

Individual

interrupt

bits

are

set,

regardless of the status of the GIE bit. The GIE bit is

cleared on reset.

The “return from interrupt” instruction, RETFIE, exits

the interrupt routine, as well as sets the GIE bit, which

re-enables interrupts.

The RB0/INT pin interrupt, the RB port change interrupt

and the TMR0 overflow interrupt flags are contained in

the INTCON register.

The peripheral interrupt flags are contained in the spe-

cial function registers PIR1 and PIR2. The correspond-

ing interrupt enable bits are contained in special

function registers PIE1 and PIE2 and the peripheral

interrupt enable bit is contained in special function reg-

ister INTCON.

When an interrupt is responded to, the GIE bit is

cleared to disable any further interrupt, the return

address is pushed onto the stack, and the PC is loaded

with 0004h. Once in the interrupt service routine, the

source(s) of the interrupt can be determined by polling

the interrupt flag bits. The interrupt flag bit(s) must be

cleared in software before re-enabling interrupts to

avoid recursive interrupts.

For external interrupt events, such as the INT pin or

PORTB change interrupt, the interrupt latency will be

three or four instruction cycles. The exact latency

depends when the interrupt event occurs. The latency

is the same for one or two cycle instructions. Individual

interrupt flag bits are set, regardless of the status of

their corresponding mask bit or the GIE bit.

Note:

Individual interrupt flag bits are set, regard-

less of the status of their corresponding

mask bit or the GIE bit.

Note:

If an interrupt occurs while the Global

Interrupt Enable (GIE) bit is being cleared,

the GIE bit may unintentionally be re-

enabled by the user’s Interrupt Service

Routine (the RETFIE instruction). The

events that would cause this to occur are:

An instruction clears the GIE bit while

an interrupt is acknowledged.

The program branches to the inter-

rupt vector and executes the interrupt

service routine.

The interrupt service routine com-

pletes the execution of the RETFIE

instruction. This causes the GIE bit to

be set (enables interrupts), and the

program returns to the instruction

after the one which was meant to dis-

able interrupts.

Perform the following to ensure that inter-

rupts are globally disabled:

LOOP BCF

INTCON, GIE

; Disable global

;

interrupt bit

BTFSC INTCON, GIE

; Global interrupt

;

disabled?

GOTO

LOOP

; NO, try again

;

Yes, continue

;

with program

;

flow

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