PIC16C765SLASHP datasheet(67/158 Pages) MICROCHIP

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DS41124A-page 67

PIC16C745/765

10.5.1.10 USB Endpoint Control Register (EPCn)

The Endpoint Control Registers contains the endpoint

control bits for each of the 6 endpoints available on

USB for a decoded address. These four bits define the

control necessary for any one endpoint. Endpoint 0

(ENDP0) is associated with control pipe 0 which is

required by USB for all functions (IN, OUT, and

SETUP). Therefore, after a USB_RST interrupt has

been received the microprocessor should set ENDPT0

to contain 06h.

USB ENDPOINT CONTROL REGISTER (UEPn: 198H-19Ah)

U-0

R/W-0

—

EP_CTL_DIS

EP_OUT_EN EP_IN_EN EP_STALL

R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

-n = Value at POR reset

bit7

bit0

bit 7-4:

Unimplemented: Read as ’0’.

bit 3-1:

EP_CTL_DIS, EP_OUT_EN, EP_IN_EN: These three bits define if an endpoint is enabled and the direc-

tion of the endpoint. The endpoint enable/direction control is defined as follows:

bit 0:

EP_STALL: When this bit is set it indicates that the endpoint is stalled. This bit has priority over all other

control bits in the Endpoint Enable register, but is only valid if EP_IN_EN=1 or EP_OUT_EN=1. Any access

to this endpoint will cause the USB to return a STALL handshake. The EP_STALL bit can be set or cleared

by the SIE. Refer to the USB 1.1 Specification, Sections 4.4.4 and 8.5.2 for more details on the STALL

protocol.

EP_CTL_DIS EP_OUT_EN

EP_IN_EN

Endpoint Enable/Direction Control

Disable Endpoint

Enable Endpoint for IN tokens only

Enable Endpoint for OUT tokens only

Enable Endpoint for IN and OUT tokens

Enable Endpoint for IN, OUT, and SETUP tokens

PIC16C765/P Datasheet(PDF) 67 Page - Microchip Technology

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