PIC16C765SLASHP datasheet(31/158 Pages) MICROCHIP

31 / 158 page

Advanced Information

DS41124A-page 31

PIC16C745/765

5.0

I/O PORTS

Some pins for these I/O ports are multiplexed with an

alternate function for the peripheral features on the

device. In general, when a peripheral is enabled, that

pin may not be used as a general purpose I/O pin.

5.1

PORTA and TRISA Registers

PORTA is a 6-bit latch.

The RA4/T0CKI pin is a Schmitt Trigger input and an

open drain output. All other RA port pins have TTL input

levels and full CMOS output drivers. All pins have data

direction bits (TRIS registers), which can configure

these pins as output or input.

Setting a TRISA register bit puts the corresponding out-

put driver in a hi-impedance mode. Clearing a bit in the

TRISA register puts the contents of the output latch on

the selected pin(s).

Reading the PORTA register reads the status of the

pins, whereas writing to it will write to the port latch. All

write operations are read-modify-write operations.

Therefore, a write to a port implies that the port pins are

read, the value is modified, and then written to the port

data latch.

Pin RA4 is multiplexed with the Timer0 module clock

input to become the RA4/T0CKI pin.

On the PIC16C745/765, PORTA pins are multiplexed

with analog inputs and analog VREF input. The opera-

tion of each pin is selected by clearing/setting the con-

trol bits in the ADCON1 register (A/D Control

Register1).

The TRISA register controls the direction of the RA

pins, even when they are being used as analog inputs.

The user must ensure the bits in the TRISA register are

maintained set when using them as analog inputs.

EXAMPLE 5-1:

INITIALIZING PORTA

(PIC16C745/765)

BCF

STATUS, RP1

;

BCF

STATUS, RP0

;

CLRF

PORTA

; Initialize PORTA by

; clearing output

; data latches

BSF

STATUS, RP0

; Select Bank 1

MOVLW

0x06

; Configure all pins

MOVWF

ADCON1

; as digital inputs

MOVLW

0xCF

; Value used to

; initialize data

; direction

MOVWF

TRISA

; Set RA<3:0> as inputs

; RA<5:4> as outputs

; TRISA<7:6> are always

; read as ’0’.

FIGURE 5-1:

BLOCK DIAGRAM OF RA<3:0>

AND RA5 PINS

FIGURE 5-2:

BLOCK DIAGRAM OF

RA4/T0CKI PIN

Note:

On all resets, pins with analog and digital

functions are configured as analog inputs.

Data

Bus

Port

TRIS

Data Latch

TRIS Latch

RD TRIS

RD PORT

VSS

VDD

I/O Pin

Analog

Input

Mode

To A/D Converter

VDD

Schmitt

Trigger

Input

Buffer

Data

Bus

PORT

TRIS

RD PORT

Data Latch

TRIS Latch

RD TRIS

Schmitt

Trigger

Input

Buffer

VSS

I/O pin

TMR0 Clock Input

VDD

PIC16C765/P Datasheet(PDF) 31 Page - Microchip Technology

PIC16C765/P Datasheet(HTML) 31 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL