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PIC16C765/P Datasheet(PDF) 125 Page - Microchip Technology |
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PIC16C765/P Datasheet(HTML) 125 Page - Microchip Technology |
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125 / 158 page ![]() © 1999 Microchip Technology Inc. Advanced Information DS41124A-page 125 PIC16C745/765 16.1 DC Characteristics: PIC16C745/765 (Commercial, Industrial) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C ≤ TA ≤ +70°C for commercial -40°C ≤ TA ≤ +85°C for industrial Param No. Sym Characteristic Min Typ† Max Units Conditions D001 VDD Supply Voltage 4.35 – 5.25 V See Figure 16-1 D002* VDR RAM Data Retention Voltage (Note 1) – 1.5 – V D003 VPOR VDD Start Voltage to ensure internal Power-on Reset signal – VSS – V See section on Power-on Reset for details D004* D004A* SVDD VDD Rise Rate to ensure inter- nal Power-on Reset signal 0.05 TBD – – – – V/mS V/mS PWRT enabled (PWRTE bit clear) PWRT disabled (PWRTE bit set) See section on Power-on Reset for details D005 VBOR Brown-out Reset voltage trip point 3.65 – 4.35 V Brown-out Reset is always active D010 D013 IDD Supply Current (Note 2, 4) TBD TBD TBD TBD TBD TBD mA FINT = 24 MHz, VDD = 4.35V FINT = 24 MHz, VDD = 5.25V D020 D021 D021B IPD Power-down Current (Note 3, 4) TBD TBD TBD TBD TBD TBD µA µA VDD = 4.35V VDD = 5.25V D022* D022A* ∆IWDT ∆IBOR ∆ICCP ∆IA/D ∆IUSB ∆IUSB ∆PLL Module Differential Current (Note 5, 6) Watchdog Timer Brown-out Reset Capture Compare PWM Analog Not suspend mode Suspend mode Phase Lock Loop – – TBD TBD TBD TBD TBD 6.0 100 TBD TBD TBD TBD TBD 20 150 TBD TBD TBD TBD TBD µA µA µA µA µA µA µA WDTE bit set, VDD = 4.35V BODEN bit set, VDD = 5.0V 1A FOSC HS oscillator operating freq. H4 oscillator operating freg. EC oscillator operating freq. E4 oscillator operating freq. 24 6 24 6 — — — — 24 6 24 6 MHz MHz MHz MHz All temperatures All temperatures All temperatures All temperatures * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consump- tion. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from characterization and is for design guidance only. This is not tested. 5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 6: Module differential currents measured at FINT = 24 MHz. |
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