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PIC16LC773-04/SP Datasheet(PDF) 123 Page - Microchip Technology

Part # PIC16LC773-04/SP
Description  28/40-Pin, 8-Bit CMOS Microcontrollers w/ 12-Bit A/D
PDF  200 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC16LC773-04/SP Datasheet(HTML) 123 Page - Microchip Technology

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PIC16C77X
© 1999 Microchip Technology Inc.
Advance Information
DS30275A-page 123
11.6
A/D Sample Requirements
11.6.1
RECOMMENDED SOURCE IMPEDANCE
The maximum recommended impedance for ana-
log sources is 2.5 k
Ω. This value is calculated based
on the maximum leakage current of the input pin. The
leakage current is 100 nA max., and the analog input
voltage cannot be vary by more than 1/4 LSb or
250 mV due to leakage. This places a requirement on
the input impedance of 250
µV/100 nA = 2.5 kΩ.
11.6.2
SAMPLING TIME CALCULATION
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 11-8. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD), see Figure 11-8. The maximum recom-
mended impedance for analog sources is 2.5 k
Ω.
After the analog input channel is selected (changed)
this sampling must be done before the conversion can
be started.
To
calculate
the
minimum
sampling
time,
Equation 11-6 may be used. This equation assumes
that 1/4 LSb error is used (16384 steps for the A/D).
The 1/4 LSb error is the maximum error allowed for the
A/D to meet its specified resolution.
The CHOLD is assumed to be 25 pF for the 12-bit
A/D.
FIGURE 11-6: A/D SAMPLING TIME EQUATION
VHOLD =(VREF - VREF/16384) = (VREF) • (1 -e
(-TC/C (RIC +RSS + RS)
) VREF(1 - 1/16384) = VREF • (1 -e
(-TC/C (RIC +RSS + RS)
)
TC = -CHOLD (1k
Ω + RSS + RS) In (1/16384)
Figure 11-7 shows the calculation of the minimum time
required to charge CHOLD. This calculation is based on
the following system assumptions:
CHOLD = 25 pF
RS = 2.5 k
Ω
1/4 LSb error
VDD = 5V
→ RSS = 10 kΩ (worst case)
Temp (system Max.) = 50
°C
Note 1: The reference voltage (VREF) has no
effect on the equation, since it cancels
itself out.
2: The charge holding capacitor (CHOLD) is
not discharged after each conversion.
3: The maximum recommended impedance
for analog sources is 2.5 k
Ω. This is
required to meet the pin leakage specifi-
cation.
4: After a conversion has completed, 2 TAD
time must be waited before sampling can
begin again. During this time the holding
capacitor is not connected to the selected
A/D input channel.



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