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PIC16LC773-04/SP Datasheet(PDF) 128 Page - Microchip Technology |
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PIC16LC773-04/SP Datasheet(HTML) 128 Page - Microchip Technology |
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128 / 200 page ![]() PIC16C77X DS30275A-page 128 Advance Information © 1999 Microchip Technology Inc. FIGURE 12-1: CONFIGURATION WORD 12.2 Oscillator Configurations 12.2.1 OSCILLATOR TYPES The PIC16C77X can be operated in four different oscil- lator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: • LP Low Power Crystal • XT Crystal/Resonator • HS High Speed Crystal/Resonator • RC Resistor/Capacitor 12.2.2 CRYSTAL OSCILLATOR/CERAMIC RESONATORS In XT, LP or HS modes, a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure 12-2). The PIC16C77X oscillator design requires the use of a par- allel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifica- tions. A difference from the other mid-range devices may be noted in that the device can be driven from an external clock only when configured in HS mode (Figure 12-3). CP1 CP0 BORV1 BORV0 CP1 CP0 - BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0 Register: CONFIG Address 2007h bit13 12 11 10 9 8 7 6 5 4 3 2 1 bit0 bit 13-12: CP1:CP0: Code Protection bits (2) bit 9-8: 11 = Program memory code protection off bit 5-4: 10 = 0800h-0FFFh code protected 01 = 0400h-0FFFh code protected 00 = 0000h-0FFFh code protected bit 11-10: BORV1:BORV0: Brown-out Reset Voltage bits(3) 11 = VBOR set to 2.5V 10 = VBOR set to 2.7V 01 = VBOR set to 4.2V 00 = VBOR set to 4.5V bit 7: Unimplemented, Read as ’1’ bit 6: BODEN: Brown-out Reset Enable bit (1) 1 = Brown-out Reset enabled 0 = Brown-out Reset disabled bit 3: PWRTE: Power-up Timer Enable bit (1) 1 = PWRT disabled 0 = PWRT enabled bit 2: WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Note 1: Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled. 2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed. 3: These are the minimum trip points for the BOR, see Table 15-4 for the trip point tolerances. Selection of an unused setting may result in an inadvertant interrupt. |
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