CC1100-RTY1 datasheet(77/100 Pages) TI1

77 / 100 page

CC1100

SWRS038D

Page 77 of 92

0x1A: BSCFG – Bit Synchronization Configuration

Bit

Field Name

Reset

R/W

Description

7:6

BS_PRE_KI[1:0]

1 (01)

R/W

The clock recovery feedback loop integral gain to be used before a sync word

is detected (used to correct offsets in data rate):

Setting

Clock recovery loop integral gain before sync word

0 (00)

1 (01)

2 (10)

3 (11)

5:4

BS_PRE_KP[1:0]

2 (10)

R/W

The clock recovery feedback loop proportional gain to be used before a sync

word is detected.

Setting

Clock recovery loop proportional gain before sync word

0 (00)

1 (01)

2 (10)

3 (11)

BS_POST_KI

R/W

The clock recovery feedback loop integral gain to be used after a sync word is

detected.

Setting

Clock recovery loop integral gain after sync word

Same as BS_PRE_KI

KI /2

BS_POST_KP

R/W

The clock recovery feedback loop proportional gain to be used after a sync

word is detected.

Setting

Clock recovery loop proportional gain after sync word

Same as BS_PRE_KP

1:0

BS_LIMIT[1:0]

0 (00)

R/W

The saturation point for the data rate offset compensation algorithm:

Setting

Data rate offset saturation (max data rate difference)

0 (00)

±0 (No data rate offset compensation performed)

1 (01)

±3.125% data rate offset

2 (10)

±6.25% data rate offset

3 (11)

±12.5% data rate offset

CC1100-RTY1 Datasheet(PDF) 77 Page - Texas Instruments

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