DP83953 datasheet(6/90 Pages) NSC

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2.0 Pin Descriptions (Continued)

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Pin Name

Pin No.

Driver

Type

I/O

Description

Processor Bus Pins

RA0 - RA4

select a register to be read or written. The state of these inputs

is ignored when the read, write and Mode Load input strobes

are high. (Even under these conditions these inputs must not be

allowed to float at an undefined logic state). See text and table

for proper Mode Load Operation strapping.

STR0

DISPLAY UPDATE STROBE 0

Maximum Display Mode: This signal controls the latching of

display data for network ports 1 to 7 into the off chip display

latches.

Minimum Display Mode: This signal controls the latching of

display data for the RIC2A into the off chip display latch.

During processor access cycles (read or write is asserted) this

signal is inactive (high).

STR1

DISPLAY UPDATE STROBE 1

Maximum Display Mode: This signal controls the latching of

display data for network ports 8 to 13 into the off chip display

latches.

Minimum Display Mode: No operation

During processor access cycles (read or write is asserted) this

signal is inactive (high).

D0 - D7

B, Z

Data Bus

Display Update Cycles: These pins become outputs providing

display data and port address information.

Processor Access Cycles: Data input or output is performed

via these pins. The read, write and mode load inputs control the

direction of the signals.See text and table for proper Mode Load

Operation strapping.

Note: The data pins remain in their display update function, i.e., asserted as out-

puts unless either the read or write strobe is asserted.

BUFEN

BUFFER ENABLE: This output controls the TRI-STATE® oper-

ation of the bus transceiver which provides the interface be-

tween the RIC2A's data pins and the processor's data bus.

Note: The buffer enable output indicates the function of the data pins. When it is

high they are performing display update cycles, when it is low a processor access

or mode load cycle is occurring.

RDY

DATA READY STROBE: The falling edge of this signal during

a read cycle indicates that data is stable and valid for sampling.

In write cycles the falling edge of RDY denotes that the write

data has been latched by the RIC2A. Therefore data must have

been available and stable for this operation to be successful.

ELI

EVENT LOGGING INTERRUPT: A low level on the ELI output

indicates the RIC2A's hub management logic requires CPU at-

tention. The interrupt is cleared by accessing the Port Event Re-

cording register or Event Counter that produced it. All interrupt

sources may be masked.

DP83953 Datasheet(PDF) 6 Page - National Semiconductor (TI)

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