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DP83953 Datasheet(PDF) 87 Page - National Semiconductor (TI) |
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DP83953 Datasheet(HTML) 87 Page - National Semiconductor (TI) |
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87 / 90 page ![]() 87 www.national.com 9.0 DC and AC Specification (Continued) CDEC TIMING REGISTER READ TIMING Note: Minimum high time between read/write cycle is 100 ns. Number Symbol Parameter Min Max Units T70 cdecpw CDEC pulse width 20 100 ns T71 cdeccdec CDEC to CDEC width 200 ns Number Symbol Parameter Min Max Units T80 T81 rdadrs rdadrh Read address setup Read address hold 0 0 ns ns T82 T83 rdabufa rdibufi Read active to BUFEN active Read inactive to BUFEN inactive 95 345 35 ns ns T84 T85 rdadatv rddath Read active to Data valid Read Data hold 245 75 ns ns T86 T87 rdardya rdirdyi Read active to RDY active Read inactive to RDY inactive 340 585 30 ns ns T88 rdw Read width 600 ns |
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