DP83953 datasheet(89/90 Pages) NSC

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9.0 DC and AC Specification (Continued)

AC Timing Test Conditions

All specifications are valid only if the mandatory isolation is employed and all differential signals are taken to be at AUI

side of the transformer.

Output Load (See Figure Below)

Note 1:

100 pF, includes scope and jig capacitance.

Note 2:

S1 = Open for timing tests for push pull outputs.

S1 = VDD for VOL test.

S1 = GND for VOH test.

S1 = VDD for High Impedance to active low and active low to High Impedance measurements.

S1 = GND for High Impedance to active high and active high to High Impedance measurements.

Capacitance TA = 25°C, f = 1 MHz

Derating Factor

Output timing are measured with a purely capacitive load for 50pF. The following correction factor can be used for other

loads: CL

≥50pF+0.3ns/pF

Note: In the above diagram, the TX+ and TX- signals are taken from the AUI side of the isolation (transformer).

Input Pulse Levels (TTL/CMOS)

GND to 3.0V

Input Rise and Fall Times (TTL/CMOS)

5ns

Input and Output Reference Levels (TTL/CMOS)

1.5V

Input Pulse Levels (Diff.)

2Vp-p

Input and Output Reference Levels (Diff.)

50% Point of the Differential

TRI-STATE Reference Levels

Float (

∆V)±0.5V

Symbol

Parameter

Typ Units

CIN

Input Capacitance

COUT Output Capacitance

Figure 27. Output Loading for the Device Under Test

DP83953 Datasheet(PDF) 89 Page - National Semiconductor (TI)