BQ76PL455APFCT datasheet(30/125 Pages) TI1

30 / 125 page

COMM+

COMM–

rec_in

start

framing

125 ns

250 ns

bq76PL455A

SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016

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The base device sends and receives data through UART at variable baud rates from 125 kb/s to 1 Mb/s. The

VBUS daisy chain operates at a fixed, nominal, data rate of 4 Mb/s using a proprietary asynchronous protocol.

Each byte is sent as 10 bits at 250 ns/bit or 2.5 µs/byte. The bottom device retransmits data from/to the

differential serial interface on the single-ended interface connected to the host system at the baud rate selected

for the single-ended serial interface. All bq76PL455As in the daisy-chain should be set to the same baud rate to

align timing between the devices.

The VBUS interface uses a modified version of the UART protocol so it can easily translate to/from the UART

protocol. Transmission of a bit requires 250 ns, including both half-bits. It is effectively a 4-MHz signal that is

phase-shift keyed, so the resulting transmission will have both 4-MHz and 2-MHz components. See Figure 18 for

additional information.

7.3.10.2 Protocol Description

The differential VBUS uses an asynchronous byte-transfer protocol with one start bit, eight data bits, and an

optional framing bit. The start bit is always a zero. Duplication of the LSB-first data occurs so that the

transmission has no DC content. A zero is transmitted as one half-bit period low followed by one half-bit period

high. Transmission of a one is as one half-bit period high followed by one half-bit period low. A framing bit of one

will cause the byte to be discarded and the byte abort flag (FAULT_COM[ABORT_H or ABORT_L]) to be set.

Since the data transmit on the differential interface as it is being received from the single-ended UART interface,

this is used to indicate that an erroneous stop bit was detected.

Each time the bq76PL455A detects a byte with a framing bit of zero, it is interpreted as a frame-initialization byte.

If the prior frame was not completed, FAULT_COM[FRAM_ERR] is set.

If detection of the start bit occurs, the receiver samples the input on the fourth clock edge to produce the bit.

Since a bit is always immediately followed by its complement, the two will be compared and the complement

error flag (FAULT_COM[COMP_ERR_H or COMP_ERR_L]) is set if they are not opposites. The first time such

an error occurs during a frame, the assumption is that the first sampling of the bit (not the complement) is the

correct one. (If this choice is incorrect, it should detect it as a CRC failure.) If such an error occurs more than

once during a frame, the fatal-complement error flag (FAULT_COM[COMP_FLT_H or COMP_FLT_L]) is set and

the frame ignored. Since the device ignores the remainder of the frame, a FRAM_ERR occurs when the next

frame arrives.

While receiving a byte, the receiver will resynchronize on every falling edge. A falling edge is expected at least

once every 3 bits. If the expected sampling point of the fourth bit does not detect a falling edge, the edge error

flag (FAULT_COM[EDGE_ERR_H or EDGE_ERR_L]) will be set and the receiver will return to idle, discarding

the frame.

If the bq76PL455A device detects eight consecutive edge errors on the low-side interface (COMM_L+/–) with no

valid bytes being received, the block will be reset in the same manner as SOFT_RESET. This allows a wakeup

tone from the chip below in the stack to cause the part to reset.

Figure 18. VBUS Data Example, 0x4E Sent

BQ76PL455APFCT Datasheet(PDF) 30 Page - Texas Instruments

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