BQ76PL455APFCT datasheet(75/125 Pages) TI1

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bq76PL455A

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SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016

Product Folder Links: bq76PL455A

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BIT

NAME

DESCRIPTION

(1)

Please see Section Window Comparator Special Considerations for additional considerations for the use of this function.

[4]

EQ_SQUEEZE_EN(1)

This bit is used to control the internal resistors connected across the VSENSE inputs, and changes the

behavior of the CBENBL register. In the event of a broken wire, applying the resistor should cause any

stored charge on the VSENSEn capacitor to bleed off.

This bit is normally used for system testing purposes. When using this feature,

CBCONFIG[BAL_CONTINUE] is typically set to '1'.

[3]

RSVD

Reserved — always write as zero

[2]

VM_MON_EN

0 = Disable VM (–5 V charge pump) monitor so the monitor ground can be measured using

CMD_VMMONSEL.

1 = Enable VM monitor so it can be measured using CMD_VMMONSEL.

This bit is normally used for self-testing purposes.

[1]

RSVD

Reserved — always write as zero.

[0]

MODULE_MON_EN

0 = Disable VMODULE monitor so the monitor ground can be measured using CMD_MODULESEL.

1 = Enable VMODULE monitor so it can be measured using CMD_MODULESEL.

This bit is normally used for self-testing purposes.

7.6.3.16 TESTCTRL 0x20–21 (32–33) Test Control

CAUTION

Do NOT run more than one test simultaneously.

BIT

NAME

DESCRIPTION

[15:10]

RSVD

Reserved — always write/read as zero.

[7:5]

ECC_TEST

0 = Do nothing.

1 = Load USER space register correctable error to ECC_TEST_RSLT(x).

2 = Load USER space register uncorrectable error to ECC_TEST_RSLT(x).

3 = Load TI space register correctable error ECC_TEST_RSLT(x).

4 = Load TI space register uncorrectable error to ECC_TEST_RSLT(x).

5–7 = Reserved

This bit is normally used for self-testing purposes.

[4]

ADC_FCAL_TEST

This test can be used to confirm the ADC is functioning properly. Test pass or fail is reported in register

FAULT_DEV[ADC_CAL_ERR] (0x61[4]).

0 = Do nothing.

1 = Perform a full calibration test of the ADC.

This bit is self-clearing and will return '1' while the test is running and '0' when it is complete.

Note: If written to '1' when ADC_PCAL_TEST is set, the device will stop the partial calibration and start

a full calibration. The ADC_PCAL_TEST bit will be cleared.

[3]

ADC_PCAL_TEST

This test can be used to confirm the ADC is functioning properly by running an abbreviated calibration

cycle and comparing the results to those stored during TI factory testing. The original results are not

overwritten.

0 = Do nothing

1 = Perform a partial calibration test of the ADC.

This bit is self-clearing and will return '1' while the test is running and '0' when it is complete.

Note: If written to ‘1’ when ADC_FCAL_TEST is set, the device will ignore the command and the

ADC_PCAL_TEST bit will be cleared.

[2]

GTSD_TRIP

This bit directly forces the thermal shutdown of the digital die to trip. Setting this bit to 1 will cause the

device to reset:

0 = Normal operation

1 = Simulate over temperature (triggers thermal shutdown)

This bit is normally used for self-testing purposes.

[1]

HTSD_TRIP

This bit directly forces the thermal shutdown of the analog die to trip. Setting this bit to 1 will cause the

device to reset:

0 = Normal operation

1 = Simulate over temperature (triggers thermal shutdown)

This bit is normally used for self-testing purposes.

BQ76PL455APFCT Datasheet(PDF) 75 Page - Texas Instruments

BQ76PL455APFCT Datasheet(HTML) 75 Page - Texas Instruments

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