BQ76PL455APFCT datasheet(73/125 Pages) TI1

73 / 125 page

bq76PL455A

www.ti.com

SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016

Product Folder Links: bq76PL455A

Submit Documentation Feedback

BIT

NAME

DESCRIPTION

[13:12]

BAUD

0 = 125 Kbaud

1 = 250 Kbaud

2 = 500 Kbaud

3 = 1 Mbaud

This register will be reset to 250 Kbaud by a communication reset.

[11:8]

RSVD

Reserved — always write/read as zero.

[7]

UART_EN

0 = Disable single-ended transmitter and FAULT_N outputs. When disabled, TX will drive high and

FAULT_N will drive low. Signals do not tri-state.

1 = Enable single-ended transmitter interface

[6]

COMM_HIGH_EN

0 = Disable high-side differential receiver interface

1 = Enable high-side differential receiver interface

[5]

DIFF_COMM_EN

0 = Disable differential low-side transmission interface

1 = Enable differential low-side transmission interface

[4]

FAULT_HIGH_EN

0 = Disable high-side fault differential receiver interface

1 = Enable high-side fault differential receiver interface

[3]

DIFF_FAULT_EN

0 = Disable differential fault output heartbeat

1 = Enable differential fault output heartbeat

[2:0]

RSVD

Reserved—Always write/read as zero.

7.6.3.12

TXHOLDOFF 0x12 (18) UART Transmitter Holdoff

BIT

NAME

DESCRIPTION

[7:0]

TX_HOLDOFF

This sets how many bit periods after a received stop bit the transmitter needs to wait before it starts to

transmit response data.

BQ76PL455APFCT Datasheet(PDF) 73 Page - Texas Instruments

BQ76PL455APFCT Datasheet(HTML) 73 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL