BQ76PL455APFCT datasheet(12/125 Pages) TI1

12 / 125 page

bq76PL455A

SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016

www.ti.com

Product Folder Links: bq76PL455A

Submit Documentation Feedback

(1)

Specified by design, not tested in production.

6.17 Digital Input/Output: Daisy Chain Vertical Bus

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOH_DCC_TX

Logic level output voltage high

Single driver loaded, ILOAD = 5 mA

VDIG

−1

VDIG

VOL_DCC_TX

Logic level output voltage low

Single driver loaded, ILOAD = 5 mA

GND

TPD

Internal propagation delay, COMML to

COMMH(1)

<60

TDCC_BIT_TIME

Diff. Comms. Bit Time(1)

250

fWAKE_TONE

WAKE TONE frequency(1)

50% duty-cycle WAKE TONE

transmitted on differential pins

COMMH+/COMMH–

100

kHz

tWAKE TONE

WAKE TONE duration(1)

WAKE TONE transmitted on differential

pins COMMH+/COMMH–

(1)

Pulses shorter than 100 µs may wake the device, but must maintain 100 µs to assure start up.

(2)

Environmental noise may affect tone detection.

(3)

Specified by design, not tested in production.

6.18 Digital Input/Output: Wakeup

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VIH_WAKEUP

WAKEUP high-input voltage

2.3

VIL_WAKEUP

WAKEUP low-input voltage

0.7

tWAKEUP_HOLD

(1)

WAKEUP hold time (high-pulse width)

Pulse driven 0-1-0

100

µs

tWAKEUP_DLY

Delay between WAKEUP pin assertion and

WAKETONE transmission

Typical application circuit with typical

components as outlined in the Application and

Implementation section.

1.2

tWAKE TONE DELAY_DC

Delay

(2) between start of WAKETONE received

and WAKETONE transmission

After POR exit condition [VDD18VO > 1.7 V] is

met.

1.2

tWAKEUP_TO_DCOMM

Required delay from WAKETONE transmission

to ready for differential communications

(3)

1.1

tWAKEUP_TO_UART

Required delay from WAKETONE transmission

to ready for UART communications

(3)

200

µs

(1)

Program EEPROM temperature (TA ) between 0°C and 30°C.

(2)

Specified by design, not tested in production.

(3)

Erase / Program cycles not to exceed EECYCLES.

6.19 EEPROM

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

EEPGM

(1)

EEPROM total program time(2)

No writes to the device are allowed

during the programming cycle

210

500

EECYCLES

Erase / Program cycles(2)

cycles

EERETN

Data retention(2)(3)

years

(1)

Normal range specification. Ranges can be extended by using the COMP_UV[CMP_TST_SHF_UV] and

COMP_OV[CMP_TST_SHF_OV] bits. See register bit description in Table 7 for additional details.

6.20 Secondary Protector – Window Comparators

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OVRANGE

Over-voltage comparator register set-point

limits

(1)

5.175

UVRANGE

Under-voltage comparator register set-point

limits

(1)

0.7

3.875

OVUVSTEP

Threshold step resolution

ERRCMP_UV

Total UV threshold error (includes

ERRVCOMP_REF_45)

Vin = 0.7 to 3.875 V

–50

ERRCMP_UV_EXT

UV threshold error when range-extend bit is set

COMP_UV[CMP_TST_SHF_UV] = 1

–100

100

ERRCOMP_OV

Total OV threshold error (includes

ERRVCOMP_REF_45)

Vin = 2 to 5.175 V

–50

ERRCOMP_OV_EXT

OV threshold error when range-extend bit is set

COMP_UV[CMP_TST_SHF_OV] = 1

–60

VCOMP_HYST

Threshold hysteresis

Hysteresis enabled;

DEVCONFIG[COMP_HYST_EN] = 1

130

BQ76PL455APFCT Datasheet(PDF) 12 Page - Texas Instruments

BQ76PL455APFCT Datasheet(HTML) 12 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL