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BQ76PL455APFCT Datasheet(PDF) 64 Page - Texas Instruments |
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BQ76PL455APFCT Datasheet(HTML) 64 Page - Texas Instruments |
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64 / 125 page  64 bq76PL455A SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016 www.ti.com Product Folder Links: bq76PL455A Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Register Maps (continued) 7.6.2 Register Summary KEY: ADDR = Address; R = Read; W = Write; R/W = Read/Write;EE = EEPROM: NA = value is volatile storage only and not included in the EEPROM; '-' indicates the location is reserved for future use; (hex value) indicates the default value programmed into the EEPROM location, that will be copied to the associated volatile register upon successful reset initialization; CSUM = Checksum: Y = value included in checksum calculation; N = value not included in calculation. Table 7. Register Summary ADDR HEX ADDR DECIMAL BITS NAME DESCRIPTION DEFAULT (HEX) R/W CSUM(3) RAM(1) EE(2) 00–01 0–1 16 SREV Silicon Revision 0806 N/A R N 02 2 8 CMD Command 00 N/A W N 03–06 3–6 32 CHANNELS Command channel select 0000 0000 FFFF 0000 R/W Y 07 7 8 OVERSMPL Command averaging (oversampling) 00 7B R/W Y 08–09 8–9 16 RESERVED Reserved for future use 00 — R/W N 0A 10 8 ADDR Device address 00 00 R/W Y 0B 11 8 GROUP_ID (Device) Group Identifier 00 00 R/W Y 0C 12 8 DEV_CTRL Device control 20 N/A R/W N 0D 13 8 NCHAN Number of channels enabled for conversion 00 10 R/W Y 0E 14 8 DEVCONFIG Device configuration 00 10 R/W Y 0F 15 8 PWRCONFIG Power configuration 00 80 R/W Y 10–11 16–17 16 COMCONFIG Communications configuration 1000 1080 R/W Y 12 18 8 TXHOLDOFF UART Transmitter holdoff 00 00 R/W Y 13 19 8 CBCONFIG Cell balancing (equalization) configuration 00 00 R/W Y 14–15 20–21 16 CBENBL Cell balancing enables 0000 N/A R/W Y 16–1D 22–29 64 RESERVED Reserved for future use 00 — R/W N 1E–1F 30–31 16 TSTCONFIG Built-In Self-Test (BIST) configuration 0000 N/A R/W Y 20–21 32–33 16 TESTCTRL BIST control 0000 N/A R/W N 22–24 34–36 24 TEST_ADC ADC BIST control 0000 N/A R/W Y 25 37 8 TESTAUXPU Test control—AUX pull-up resistors 00 N/A R/W Y 26–27 38–39 16 RESERVED Reserved for future use 00 — R/W N 28 40 8 CTO Communications time-out 00 DC R/W Y 29–2B 41–43 24 CTO_CNT Communications time-out counter 0000 N/A R/W N 2C–31 44–49 40 RESERVED Reserved for future use 0000 — R/W N 32 50 8 00 0 R/W Y 33–36 51–54 32 0000 0000 R/W Y 37 55 8 00 00 R/W Y 38–3C 56–60 40 RESERVED Reserved for future use 0000 — R/W N 3D 61 8 SMPL_DLY1 Initial sampling delay 00 0 R/W Y 3E 62 8 CELL_SPER Cell and die temperature measurement period 00 BC R/W Y 3F–42 63–66 32 AUX_SPER AUX channels sampling period 0000 0000 4444 4444 R/W Y 43–44 67–68 16 TEST_SPER ADC test sampling period 0000 F999 R/W Y 45–4F 69–79 88 RESERVED Reserved for future use 00 — R/W N 50 80 8 SHDN_STS Shutdown recovery status 00 N/A R N 51 81 8 STATUS Device status 81(4) N/A R/W N 52–53 82–83 16 FAULT_SUM Fault summary 0100(4) N/A R/W N 54–55 84–85 16 FAULT_UV Undervoltage faults 0000(4) N/A R/W N 56–57 86–87 16 FAULT_OV Overvoltage faults 0000(4) N/A R/W N 58–59 88–89 16 FAULT_AUX AUX threshold exceeded faults 0000(4) N/A R/W N 5A–5B 90–91 16 FAULT_2UV Comparator UV faults 0000(4) N/A R/W N |
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