BQ76PL455APFCT datasheet(91/125 Pages) TI1

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bq76PL455A

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SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016

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7.6.3.71 VSOFFSET 0xD2 (210) Cell Offset Correction

BIT

NAME

DESCRIPTION

[7:0]

CCOFFSET

User offset-adjustment register for VSENSE cell voltage channels. This 2's complement value will be

added to all cell voltage channels. The range is approximately –9.77 mV to 9.69 mV in 255 steps.

The offset is approximately equal to (5 V × CCOFFSET / 216). It can be used to compensate for

offsets induced by the user design or PCB mounting.

7.6.3.72 VSGAIN 0xD3 (211) Cell Gain Correction

BIT

NAME

DESCRIPTION

[7:0]

CCGAIN

User gain-adjustment register for VSENSE cell voltage channels. This is a 2's complement value

where positive values represent a gain > 1.0 and negative values represent a gain < 1.0, and is

applied to all cell voltage channels.

The range is approximately –9.77 mV to 9.69 mV full scale in 255 steps. The gain correction is

approximately equal to (input value × (1 + CCGAIN / 216)). It can be used to compensate for gain

error induced by the user design (such as larger values of input resistor) or PCB mounting.

7.6.3.73 AX0OFFSET 0xD4–D5 (212–213) AUX0 Offset Correction

BIT

NAME

DESCRIPTION

[15:10]

RSVD

Reserved — always write/read as zero

[9:0]

AUX_COFFSET0

User offset-adjustment register for AUX0 input. This 2's complement value will be added to the AUX

channel. The range is approximately –38.99 mV to 39.06 mV full scale in 1023 steps. The offset is

approximately equal to (5 V × AUXCOFFSET0 / 216). See Section AUX Channel Post-Assembly

Calibration Adjustment for details. It can be used to compensate for offsets induced by the user

design or PCB mounting.

7.6.3.74 AX1OFFSET 0xD6–D7 (214–215) AUX1 Offset Correction

BIT

NAME

DESCRIPTION

[15:10]

RSVD

Reserved — always write/read as zero

[9:0]

AUX_COFFSET1

User offset-adjustment register for AUX0 input. This 2's complement value will be added to the AUX

channel. The range is approximately –38.99 mV to 39.06 mV full scale in 1023 steps. The offset is

approximately equal to (5 V × AUXCOFFSET1 / 216). See Section AUX Channel Post-Assembly

Calibration Adjustment for details. It can be used to compensate for offsets induced by the user

design or PCB mounting.

7.6.3.75 AX2OFFSET 0xD8–D9 (216–217) AUX2 Offset Correction

BIT

NAME

DESCRIPTION

[15:10]

RSVD

Reserved — always write/read as zero

[9:0]

AUX_COFFSET2

User offset-adjustment register for AUX0 input. This 2's complement value will be added to the AUX

channel. The range is approximately –38.99 mV to 39.06 mV full scale in 1023 steps. The offset is

approximately equal to (5 V × AUXCOFFSET2 / 216). See Section AUX Channel Post-Assembly

Calibration Adjustment for details. It can be used to compensate for offsets induced by the user

design or PCB mounting.

7.6.3.76 AX3OFFSET 0xDA–DB (218–219) AUX3 Offset Correction

BIT

NAME

DESCRIPTION

[15:10]

RSVD

Reserved — always write/read as zero

[9:0]

AUX_COFFSET3

User offset-adjustment register for AUX0 input. This 2's complement value will be added to the AUX

channel. The range is approximately –38.99 mV to 39.06 mV full scale in 1023 steps. The offset is

approximately equal to (5 V × AUXCOFFSET3 / 216). See Section AUX Channel Post-Assembly

Calibration Adjustment for details. It can be used to compensate for offsets induced by the user

design or PCB mounting.

BQ76PL455APFCT Datasheet(PDF) 91 Page - Texas Instruments

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