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BQ76PL455APFCT Datasheet(PDF) 85 Page - Texas Instruments |
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BQ76PL455APFCT Datasheet(HTML) 85 Page - Texas Instruments |
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85 / 125 page  85 bq76PL455A www.ti.com SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016 Product Folder Links: bq76PL455A Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated BIT NAME DESCRIPTION [11] HREF_GND_FAULT Write '1': Reset the fault condition. Write '0': No effect Read '1': Analog-die reference ground measurement was out of range. [10:5] RSVD Reserved — always read as zero [4] ADC_CAL_ERR Write '1': Reset the fault condition. Write '0': No effect Read '1': An ADC test (ADC_FCAL_TEST or ADC_PCAL_TEST) failed. [3] USER_ECC_COR Write '1': Reset the fault condition. Write '0': No effect Read '1': A ECC fault was corrected while loading user space from EEPROM. [2] USER_ECC_ERR Write '1': Reset the fault condition. Write '0': No effect Read '1': An uncorrectable ECC fault was detected while loading from EEPROM. Registers in the block (not all registers) have been loaded with their default values. [1] FACT_ECC_COR Write '1': Reset the fault condition. Write '0': No effect Read '1': A ECC fault was corrected while loading factory space from EEPROM. [0] FACT_ECC_ERR Write '1': Reset the fault condition. Write '0': No effect Read '1': An uncorrectable ECC fault was detected while loading from factory registers. Registers in the block (not all registers) have been loaded with their default values. The device is operating abnormally and has probably failed. Functionality, behavior, and results are suspect and should not be relied upon. 7.6.3.36 FAULT_GPI 0x63 (99) GPI Fault BIT NAME DESCRIPTION [7:6] RSVD Reserved — always read as zero. [5:0] GPI_FAULT Write '1': Reset the fault condition. Write '0': No effect Read '1': A GPIO input, configured as a fault input in GPI_FAULT_CONFIG, has signaled a fault condition. If UNLATCHED_FAULT is set, this register is self-clearing. 7.6.3.37 MASK_COMM 0x68–69 (104–105) Communications Fault Masks BIT NAME DESCRIPTION [15] COMP_ERR_H_MSK For each of these bits: 0 = Do not mask this fault. 1 = Mask this fault. [14] COMP_ERR_L_MSK [13] COMP_FLT_H_MSK [12] COMP_FLT_L_MSK [11] EDGE_ERR_H_MSK [10] EDGE_ERR_L_MSK [9] ABORT_H_MSK [8] ABORT_L_MSK [7] CRC_FAULT_H_MSK [6] CRC_FAULT_L_MSK [5] FRAM_ERR_MSK [4] RSVD Reserved — always write/read as zero [3] STOP_ERR_MSK 0 = Do not mask this fault. 1 = Mask this fault. |
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