CS5530A datasheet(20/259 Pages) AMD

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AMD Geode™ CS5530A Companion Device Data Book

Signal Definitions

Revision 1.1

Figure 3-1.

CS5530A Signal Groups (Continued)

3.1

Pin Assignments

The tables in this section use several common abbrevia-

tions. Table 3-1 lists the mnemonics and their meanings.

Figure 3-2 shows the pin assignment for the CS5530A with

Tables 3-2 and 3-3 listing the pin assignments sorted by pin

number and alphabetically by signal name, respectively.

In Section 3.2 "Signal Descriptions" on page 29 a descrip-

tion of each signal within its associated functional group is

provided.

In the signal definitions, references to F0-F4, F1BAR,

F2BAR, F3BAR, F4BAR, and PCIUSB are made. These

terms relate to designated register spaces. Refer to Table

5-1 "PCI Configuration Address Register (0CF8h)" on page

144 for details regarding these register spaces and their

access mechanisms.

EXTVREFIN

IOUTG

IOUTB

AVSS1-5

IOUTR

AVDD1-3

HSYNC_OUT

HSYNC

VSYNC

FP_DATA17 (MASTER#)

FP_CLK (No Function)

Display: CRT

VSYNC_OUT

DDC_SCL

DDC_SDA

FP_HSYNC_OUT (SMEMW#)

FP_CLK_EVEN (No Function)

FP_VSYNC_OUT (SMEMR#)

IREF

FP_DISP_ENA_OUT (No Function)

FP_ENA_VDD (No Function)

FP_ENA_BKL (No Function)

FP_HSYNC (No Function)

FP_VSYNC (No Function)

Analog

Display: MPEG

PLLDVD

PLLVAA

DCLKPLL

Analog

PLLAGD

PLLDGN

VID_RDY

VID_VAL

VID_CLK

VID_DATA[7:0]

SA[19:16]

(SA_DIR) SA_LATCH

SBHE#

BALE

IOCHRDY

ZEROWS#

IOR#

IOW#

MEMCS16#

MEMR#

MEMW#

AEN

DRQ[7:5], [3:0]

DACK#[7:5], [3:0]

IRQ[15:14], [12:9], [7:3], 1

ISA Bus

IRQ8#

IOCS16#

(SD[15:0]) SA[15:0]/SD[15:0]

GPCS#

GPORT_CS#

(SA[23:20]) GPIO[7:4]/SA[23:20]

GPIO[3:2]

GPIO1/SDATA_IN2

GPIO0

Game Port/

GPIO

SMEMW#/RTCCS#

SMEMR#/RTCALE

FP_DATA16 (SA_OE#)

FP_DATA[15:0] (SA[15:0])

External RTC

Display: TFT/TV

Table 3-1. Pin Type Definitions

Mnemonic

Definition

Input pin1

All buffers are 5 volt tolerant.

I/O

Bidirectional pin1,2

All digital bidirectional and output pins can be TRI-STATE sig-

nals unless a weak pull-up is enabled.

Output pin1, 2

Open-drain output structure that allows multiple

devices to share the pin in a wired-OR configura-

tion

Pull-up resistor

SMT

Schmitt Trigger

VDD (PWR)

Power pin

VSS (GND)

Ground pin

The “#” symbol at the end of a signal name indi-

cates that the active, or asserted state occurs

when the signal is at a low voltage level. When

“#” is not present after the signal name, the sig-

nal is asserted when at a high voltage level.

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