CS5530A datasheet(65/259 Pages) AMD

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AMD Geode™ CS5530A Companion Device Data Book

Power Management

Revision 1.1

Index 96h

Suspend Configuration Register (R/W)

Reset Value = 00h

7:5

Reserved: Set to 0.

Power Savings: 0 = Enable; 1 = Disable.

Include ISA Clock in Power Savings Mode: 0 = ISA clock not included; 1 = ISA clock included.

Suspend Mode Configuration: “Special 3 Volt Suspend” mode to support powering down a GX1 processor during Sus-

pend. 0 = Disable; 1 = Enable.

SMI Speedup Configuration: Selects how Suspend Modulation function reacts when an SMI occurs.

0 = Use the IRQ Speedup Timer Count Register (F0 Index 8Ch) to temporarily disable Suspend Modulation when an SMI

occurs.

1 = Disable Suspend Modulation when an SMI occurs until a read to the SMI Speedup Disable Register (F1BAR+Memory

Offset 08h).

The purpose of this bit is to disable Suspend Modulation while the CPU is in the System Management Mode so that VSA

technology and power management operations occur at full speed. Two methods for accomplishing this are either to map

the SMI into the IRQ Speedup Timer Count Register (F0 Index 8Ch), or to have the SMI disable Suspend Modulation until

the SMI handler reads the SMI Speedup Disable Register (F1BAR+Memory Offset 08h). The latter is the preferred method.

The IRQ speedup method is provided for software compatibility with earlier revisions of the CS5530A. This bit has no effect

if the Suspend Modulation feature is disabled (bit 0 = 0).

Suspend Modulation Feature: 0 = Disable; 1 = Enable.

When enabled, the SUSP# pin will be asserted and deasserted for the durations programmed in the Suspend Modulation

OFF/ON Count Registers (F0 Index 94h/95h).

F0 Index A8h-A9h

Video Overflow Count Register (R/W)

Reset Value = 0000h

15:0

Video Overflow Count: Each time the Video Speedup timer (F0 Index 8Dh) is triggered, a 100 ms timer is started. If the

100 ms timer expires before the Video Speedup timer lapses, the Video Overflow Count Register increments and the 100

ms timer re-triggers. Software clears the overflow register when new evaluations are to begin. The count contained in this

F1BAR+Memory Offset 08h-09h

SMI Speedup Disable Register (Read to Enable)

Reset Value = 0000h

15:0

SMI Speedup Disable: If bit 1 in the Suspend Configuration Register is set (F0 Index 96h[1] = 1), a read of this register

invokes the SMI handler to re-enable Suspend Modulation.

The data read from this register can be ignored. If the Suspend Modulation feature is disabled, reading this I/O location has

no effect.

Table 4-14. Suspend Modulation Related Registers (Continued)

Bit

Description

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