CS5530A datasheet(14/259 Pages) AMD

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AMD Geode™ CS5530A Companion Device Data Book

Architecture Overview

Revision 1.1

2.2

PCI Bus Interface

The CS5530A provides a PCI bus interface that is both a

slave for PCI cycles initiated by the CPU or other PCI mas-

ter devices, and a non-preemptable master for DMA trans-

fer cycles. The chip also is a standard PCI master for the

IDE controllers and audio I/O logic. The CS5530A supports

positive decode for configurable memory and I/O regions

and implements a subtractive decode option for unclaimed

PCI accesses. The CS5530A also generates address and

data parity and performs parity checking. The CS5530A

does not include the PCI bus arbiter, which is located in the

processor.

Configuration registers are accessed through the PCI inter-

face using the PCI Bus Type 1 configuration mechanism as

described in the PCI 2.1 Specification.

2.3

ISA Bus Interface

The CS5530A provides an ISA bus interface for unclaimed

memory and I/O cycles on PCI. The CS5530A is the

default subtractive decoding agent and forwards all

unclaimed memory and I/O cycles to the ISA interface;

however, the CS5530A may be configured to ignore either

I/O, memory, or all unclaimed cycles (subtractive decode

disabled).

The CS5530A supports two modes on the ISA interface.

The default mode, Limited ISA Mode, supports the full

memory and I/O address range without ISA mastering. The

address and data buses are multiplexed together, requiring

an external latch to latch the lower 16 bits of address of the

ISA cycle. The signal SA_LATCH is generated when the

data on the SA/SD bus is a valid address. Additionally, the

upper four address bits, SA[23:20], are multiplexed on

GPIO[7:4].

The second mode, ISA Master Mode, supports ISA bus

masters and requires no external circuitry. When the

CS5530A is placed in ISA Master Mode, a large number of

pins are redefined. In this mode, the CS5530A cannot sup-

port TFT flat panels or TV controllers since most of the sig-

nals used to support these functions have been redefined.

This mode is required if ISA slots or ISA masters are used.

ISA master cycles are only passed to the PCI bus if they

access memory. I/O accesses are left to complete on the

ISA bus.

For further information regarding mode selection and oper-

ational details refer to Section 4.5.2.2 "Limited ISA and ISA

Master Modes" on page 92.

2.4

AT Compatibility Logic

The CS5530A integrates:

• Two 8237-equivalent DMA controllers with full 32-bit

addressing

• Two 8259-equivalent interrupt controllers providing 13

individually programmable external interrupts

• An 8254-equivalent timer for refresh, timer, and speaker

logic

• NMI control and generation for PCI system errors and all

parity errors

• Support for standard AT keyboard controllers

• Positive decode for the AT I/O register space

• Reset control

2.4.1

DMA Controller

The CS5530A supports the industry standard DMA archi-

tecture using two 8237-compatible DMA controllers in cas-

caded configuration. CS5530A-supported DMA functions

include:

• Standard seven-channel DMA support

• 32-bit address range support via high page registers

• IOCHRDY extended cycles for compatible timing

transfers

• ISA bus master device support using cascade mode

2.4.2

Programmable Interval Timer

The CS5530A contains an 8254-equivalent programmable

interval timer. This device has three timers, each with an

input frequency of 1.193 MHz.

2.4.3

Programmable Interrupt Controller

The CS5530A contains two 8259-equivalent programmable

interrupt controllers (PICs), with eight interrupt request

lines each, for a total of 16 interrupts. The two controllers

are cascaded internally, and two of the interrupt request

inputs are connected to the internal circuitry. This allows a

total of 13 externally available interrupt requests.

Each CS5530A IRQ signal can be individually selected as

edge- or level-sensitive. The PCI interrupt signals are

routed internally to the PICs IRQs.

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