CS5530A datasheet(32/259 Pages) AMD

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AMD Geode™ CS5530A Companion Device Data Book

Signal Definitions

Revision 1.1

GNT#

D24

PCI Bus Grant

GNT# is asserted by an arbiter that indicates to the CS5530A that access to

the PCI bus has been granted.

GNT# should connect to GNT0# of the GX1 processor and function as the

highest-priority PCI master.

HOLD_REQ#

H26

Strap

Option

PCI Bus Hold Request

This pin’s function as HOLD_REQ# is no longer applicable.

Strap Option Select Pin

Pin H26 is a strap option select pin. It allows selection of which address bits

are used as the IDSEL.

Strap pin H26 low: IDSEL = AD28 (Chipset Register Space) and AD29 (USB

Strap pin H26 high: IDSEL = AD26 (Chipset Register Space) and AD27

(USB Register Space)

FRAME#

C23

I/O

PCI Cycle Frame

FRAME# is asserted to indicate the start and duration of a transaction. It is

deasserted on the final data phase.

FRAME# is an input when the CS5530A is a PCI slave.

IRDY#

B24

I/O

PCI Initiator Ready

IRDY# is driven by the master to indicate valid data on a write transaction, or

that it is ready to receive data on a read transaction.

When the CS5530A is a PCI slave, IRDY# is an input that can delay the

beginning of a write transaction or the completion of a read transaction.

Wait cycles are inserted until both IRDY# and TRDY# are asserted together.

TRDY#

B23

I/O

PCI Target Ready

TRDY# is asserted by a PCI slave to indicate it is ready to complete the cur-

rent data transfer.

TRDY# is an input that indicates a PCI slave has driven valid data on a read

or a PCI slave is ready to accept data from the CS5530A on a write.

TRDY# is an output that indicates the CS5530A has placed valid data on

AD[31:0] during a read or is ready to accept the data from a PCI master on a

write.

Wait cycles are inserted until both IRDY# and TRDY# are asserted together.

STOP#

E26

I/O

PCI Stop

As an input, STOP# indicates that a PCI slave wants to terminate the current

transfer. The transfer is either aborted or retried. STOP# is also used to end

a burst.

As an output, STOP# is asserted with TRDY# to indicate a target discon-

nect, or without TRDY# to indicate a target retry. The CS5530A asserts

STOP# during any cache line crossings if in single transfer DMA mode or if

busy.

3.2.4

PCI Interface (Continued)

Signal Name

No.

Type

Description

CS5530A Datasheet(PDF) 32 Page - Advanced Micro Devices

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